Abstract: A power management module comprising a client monitoring component arranged to monitor idle periods for a client component, and derive at least one idle period characteristic value for the client component based at least partly on the monitoring of the idle periods therefore. The power management module further comprises a power mode control component arranged to receive an indication of the client component entering an idle state, cause the client component to be put into a reduced power mode upon expiry of a first period of time, and cause the client component to be brought out of the reduced power mode upon expiry of a second period of time. At least one of the first and second periods of time is configured based at least partly on the idle period characteristic value(s) derived by the client monitoring component for the client component.

Abstract: A non-isolated capacitive AC-DC conversion power supply includes a current limiting input module that receives AC input power and has an output capacitor that supplies DC power. Charge storage stages have charge storage capacitors, a rectifier supplying rectified current from the input module to charge the charge storage capacitors and the output capacitor during a first part-cycle of the AC input power. The charge storage stages also include current amplifiers and unidirectional elements that conduct discharge current from the charge storage capacitors to charge the output capacitor during a second part-cycle of the AC input power. Ground of the DC output can be connected to the live AC input.

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Abstract: Each task assigned to a core can be considered an “active” task. Sequential strobe signals of a watchdog signal can be spaced apart in time by a certain duration. The duration between strobe signals is longer than the expected duration of an active task. By knowing that all tasks being monitored are expected to execute within an expected amount of time, the duration between the strobe signals can be set to be longer than that expected amount of time. If a task has not transitioned to inactive by a next strobe, a watchdog error has occurred.

Abstract: A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body

Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Abstract: A CML latch includes an input stage including input nodes to receive a differential input signal and output nodes to provide a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal, a negative resistance stage including an input node connected to a first voltage source and output nodes connected to the output nodes of the input stage, and a latch stage including input nodes connected to the output nodes of the input stage and output nodes to provide a differential output signal. The negative resistance stage increases a current gain of the input stage.

Abstract: An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).

Abstract: The present application relates an encoder. The encoder partitions an image domain into several substructures each having one of at least one size dimension, and defines at least one geometric primitive for each substructure on the basis of geometry data. The encoder also retrieves, for each substructure, a subset of image data and determines whether pixel values of the retrieved subset are the same. If the pixel values are describable by a texture mapping operation, then the encoder defines a compressed texture image and assigns texture mapping data to the geometry data. Otherwise, the encoder defines an uncompressed texture image and assigns texture mapping data to the geometry data. The compressed image includes the geometry data, the texture mapping data, and the texture image data.

Abstract: A tunable clock circuit has a dual overlapping digital to analog converter (DAC) and an oscillator. The dual overlapping DAC provides a first output selectable with a first resolution and a second output selectable with a second resolution. The first resolution is different from the second resolution. The oscillator has a first input coupled to the first output of the dual overlapping DAC, a second input coupled to the second output of the dual overlapping DAC, and an output providing a clock output signal.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.

Abstract: An EDA tool for validating predefined timing paths having corresponding timing constraints in an integrated circuit (IC) design has a processor that performs a static-timing-analysis (STA) of the IC design and generates a STA report that includes the first set of timing constraints, which include a first number of clock cycles required for propagating the first multi-cycle timing path. A simulation-based checker based on a STA that counts a second number of clock cycles that is actually required by the first multi-cycle timing path to propagate is generated while performing a unit-delay, gate-level netlist simulation of the first-multiple cycle timing path. The first set of timing constraints then are modified so that the first multi-cycle timing path is redefined to require the second number of clock cycles to propagate.

Abstract: An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.

Abstract: A direct-sequence spread spectrum signal receiving device may comprise a receiver unit, a chip sequence generating unit, a correlation unit, and comparison unit. The receiver unit may extract a chip stream from a radio-frequency signal, said chip stream containing a first chip sequence. The chip sequence generating unit may generate a plurality of trial chip sequences on the basis of a first trial chip sequence and on the basis of a plurality of index rotations. The correlation unit may determine a plurality of correlation values on the basis of said plurality of trial chip sequences and on the basis of said first chip sequence, each of said correlation values indicating a degree of correlation between a respective one of said trial chip sequences and said first chip sequence. The comparison unit may determine whether a maximum one of said correlation values exceeds a defined threshold value.

Abstract: A semiconductor device includes a lead frame, and an integrated circuit die. The lead frame has a flag for supporting the die and leads that surround that flag and die. The lead frame also has ground ring that surrounds the flag and die. First bond wires electrically connect the die to the lead frame leads. An insulating layer is disposed on the ground ring, and a power layer is disposed on the insulating layer. The semiconductor device further includes second bond wires that connect the die to the ground ring and third bond wires that connect the die to the power layer.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.

Abstract: A method and apparatus for an asynchronous multicore common debugging system is described. Debug signals from a plurality of processor cores are synchronized to a common timing domain. Processing completed within the plurality of processor cores during a common timing interval is tracked. A single debugging tool chain is utilized to provide debugging results in response to the tracking the processing completed within the plurality of processor cores during the common timing interval.

Abstract: An integrated circuit (IC) includes a power grid having first, through fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively, a voltage regulator, a reference voltage calibration circuit, a dual-rail sense circuit, and a voltage monitor circuit. The reference voltage calibration circuit receives the first supply, first ground, second supply, and second ground voltage signals and generates a reference voltage signal based on differences between voltage levels of the first supply and ground voltage signals, and the second supply and ground voltage signals. The voltage regulator regulates the first supply voltage signal based on the reference voltage signal and the second supply voltage signal. The dual-rail sense circuit generates a sense signal based on the second supply and ground voltage signals. The voltage monitor generates a voltage monitor signal based on the sense signal that indicates a state of the IC.