Abstract: A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.

Abstract: A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.

Abstract: The embodiments described herein provide inverse class F (class F?1) amplifiers. In general, the inverse class F amplifiers are implemented with a transistor, an output inductance and a transmission line configured to approximate inverse class F voltage and current output waveforms by compensating the effects of the transistor's intrinsic output capacitance for some even harmonic signals while providing a low impedance for some odd harmonic signals. Specifically, the transistor is configured with the output inductance and transmission line to form a parallel LC circuit that resonates at the second harmonic frequency. The parallel LC circuit effectively creates high impedance for the second harmonic signals, thus blocking the capacitive reactance path to ground for those harmonic signals that the intrinsic output capacitance would otherwise provide. This facilitates the operation of the amplifier as an effective, high efficiency, inverse class F amplifier.

Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.

Abstract: A thermal sensor system including at least one thermal sensor, a voltage control network, a current gain network, a current compare sensor, and a controller. The voltage control network applies reference and delta voltage levels to a thermal sensor, which develops reference and delta current signals. The current gain network is used to adjust current gain. The current compare sensor is responsive to the reference and delta current signals and provides a comparison metric. The controller selects a temperature subrange and controls the current gain network to adjust the gain of the delta current signal to determine a gain differential value indicative of the temperature. The controller may select from among different sized thermal sensors, current mode gain values, and control voltages corresponding with each of multiple temperature subranges. Any one or more of these parameters may be adjusted to adjust an operating point for selecting a corresponding temperature subrange.

Abstract: In accordance with at least one embodiment, a clock counter on a system (for example, a system-on-a-chip (SOC) or other system) is utilized to count a number of a clock edges of a memory clock within a predefined time based on a predetermined system clock frequency and, therefore, to determine whether the memory clock for a memory array (for example, a non-volatile memory (NVM) array or other memory array) is correct or not. The system is directed to wait until the count is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the system such that the application can react to it.

Abstract: A memory device can include an array of NOR memory cells, each memory cell including a floating gate, a source on a source side of the floating gate, a drain on a drain side of the floating gate, a drain contact on the drain, and a source contact on the source. The source contacts are connected to a common source line. A plurality of bit lines are connected to respective drains in a column of the memory cells. A plurality of word lines, each word line coupled to respective floating gates in a row of the memory cells. Spacing between the word lines on the drain side is greater than spacing between the word lines on the source side.

Abstract: An apparatus (36) includes a motion amplification structure (52), an actuator (54), and a sense electrode (50) in proximity to the structure (52). The actuator (54) induces an axial force (88) upon the structure (52), which causes a relatively large amount of in-plane motion (108) in one or more beams (58, 60) of the structure (52). When sidewalls (98) of the beams (58, 60) exhibit a skew angle (28), the in-plane motion (108) of the beams (58, 60) produces out-of-plane motion (110) of a paddle element (62) connected to the end of the beams (58, 60). The skew angle (28), which results from an etch process, defines a degree to which the sidewalls (98) of beams (58, 60) are offset or tilted from their design orientation. The out-of-plane motion (110) of element (62) is sensed at the electrode (50), and is utilized to determine an estimated skew angle (126).

Abstract: A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops.

Abstract: A method and circuit for generating ramped voltages are provided. The ramp voltage generator circuit includes: a switched-capacitor amplifier having an input terminal, an output terminal, a sampling capacitor switchably coupled to the input terminal, and a gain capacitor switchably coupled to the output terminal; and a current source having a terminal coupled to a supply terminal, and a terminal coupled to the input terminal. The ramp voltage generator circuit may be coupled to test an analog-to-digital converter (ADC).

Abstract: A driver circuit for testing a saturation level in an insulated gate bipolar transistor (“IGBT”) includes a comparator having a first input coupled to a reference voltage and a second input coupled to a saturation test node, and a first transistor having a first current electrode coupled to the first input of the comparator, a second current electrode coupled to a supply voltage, and a control electrode coupled to a first output of a test circuit. The first output is associated with a test initiation function of an internal test process. A second transistor has a first current electrode coupled to a control electrode of the IBGT transistor, a second current electrode coupled to the supply voltage, and a control electrode coupled to a second output of the test circuit. The second output is associated with an over-current indication of the internal test process.

Abstract: An apparatus comprising: at least one processor; and at least one memory including computer program code; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus at least to perform static code analysis of a plurality of instructions comprising, for each instruction: determining whether a trace message is generated by the instruction; determining whether a size of the trace message generated by the instruction is dependent on a context; determining a size of the trace message generated by the instruction; and updating the context; and to perform determining a cumulative size of trace messages generated by the plurality of instructions.

Abstract: A data management system comprises a trie data structure. The trie data structure comprises a plurality of interconnected nodes wherein at least a portion of said plurality of interconnected nodes is configured as parent nodes and child nodes, wherein at least one child node comprises an identifier of its parent node.

Abstract: An apparatus comprising: a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and a higher-layer decoder configured to decode the first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising: synchronisation logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronisation event; and decoding logic configured to use the synchronisation event to synchronise decoding of the received first data stream to produce the trace data.

Abstract: A system comprises a mechanical resonator; an analog circuit operably coupled to the mechanical resonator; the analog circuit arranged to receive a mechanical resonator measurement signal and to output a mechanical resonator actuation signal to the mechanical resonator; and a digital actuator operably coupled to the analog circuit and configured to provide a frequency sweep of signals to the analog circuit that induces movement of the mechanical resonator.

Abstract: A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral. A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.

Abstract: A telecommunication receiver is arranged for receiving related data originating from multiple antennas, which data have different times of arrival due to, for example, different delays. The receiver comprises an input buffer for buffering data, a transform unit for Fourier transforming the data received from the input buffer into transformed data, and an output buffer for buffering the transformed data received from the transform unit. The input buffer is arranged for passing each set of data items to the transform unit when the relevant data item has been received in the input buffer, while the transform unit is arranged for removing redundant parts of the data. In addition, the output buffer is arranged for synchronizing the transformed data. Thus the buffering for delay compensation is carried out in the output buffer.

Abstract: The present application relates to a networking device with multi-MAC manager and a method of operating thereof. The multi-MAC manager receiving a request issued in the context of a medium access control, MAC, instance, determines the MAC, instance, to which the request relates and determines whether the PHY part is available for allocation or already allocated to the MAC instance. If the PHY is available, at least the PHY part of the communications interface is allocated to the MAC instance and the received request is passed to the PHY part for further processing thereat. At least the allocated PHY part is released once a service requested by the received request is completed.

Abstract: A safety system comprising: a safety apparatus adapted to be mounted at the rear of a bicycle and comprising a processor, a motion sensor, a threat sensing device and a user alert device, all coupled to the processor, wherein the processor is adapted to: control the driver alert device based on a threat position value and/or the threat speed value; control the user alert device based on at least one of a motion-based value, an ambient light-based value, the threat position value and the threat speed value. It is also claimed the safety apparatus and a collaborative safety system comprising a plurality of safety systems, each being coupled to a communication device through which the processor is further adapted to control the driver alert device and/or the user alert device of the others of the plurality in response to the sensing of a threat.

Abstract: A radar device comprises at least one transmitter unit for transmitting a radar signal, at least one receiver unit for receiving a reflected radar signal, and a phase shift unit for producing a phase shift in the frequency modulated radar signal in response to a phase shift signal. The receiver unit comprises at least one filter unit for filtering the received signal and is arranged for resetting the filter unit in response to said phase shift signal, so as to avoid saturation of the filter unit due to the phase shift.