Abstract: A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode.

Abstract: A level shifting circuit that includes a level shifter and a circuit stage. The circuit stage includes a pair of diodes circuits. The circuit stage includes a first output node and a second output node. The first output node is coupled via a current path to a first output of the level shifter and the second output node is coupled to via a current path to a second output of the level shifter. One of the diodes is coupled to the first output node and a power supply terminal. The other diode is coupled to the second output node and the power supply terminal.

Abstract: Systems and methods for reducing the power consumption of memory devices. A method of operating a memory device may include monitoring a plurality of sense amplifiers, each sense amplifier configured to evaluate a logic value stored in a memory cell, determining whether each of the plurality of sense amplifiers has completed its evaluation, and stopping a reference current from being provided to the sense amplifiers in response to all of the sense amplifiers having completed their evaluations. An electronic circuit may include memory cells, sense amplifiers coupled to the memory cells, transition detection circuits coupled to the sense amplifiers, and control circuitry coupled to the transition detection circuits, the transition detection circuits configured to stop a reference current from being provided to the sense amplifiers if each transition detection circuit determines that its respective sense amplifier has identified a logic value stored in a respective memory cell.

Abstract: Systems and methods for indicating internal transmitter errors in a Controller Area Network (CAN). In some embodiments, a method may include initiating, by a device coupled to a CAN, transmission of a message via the CAN; detecting an error by the device during the transmission; and continuing, by the device after having detected the error, the transmission of the message without causing or indicating a bus error condition. In other embodiments, a CAN node may include message processing circuitry configured to receive a frame from a transmitter, the frame comprising a cyclic redundancy check (CRC) field, the message processing circuitry further configured to identify an internal error of the transmitter based upon the CRC field.

Abstract: A stacked microelectronic package can comprise a package body having an external vertical package sidewall, a plurality of microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the external vertical package sidewall. A cavity is formed on an external surface of the package body between a first one of the package edge conductors and a second one of the package edge conductors. Electrically conductive material is in the cavity and in electrical contact with a first and a second one of the package edge conductors, wherein the conductive material in the cavity is within planform dimensions of the microelectronic package.

Abstract: An integrated circuit package has a first side and an opposite second side. The integrated circuit package comprises: a stack of layers comprising at least a first and second electrically isolating layers, a dielectric material arranged on the stack of layers at the second side for encapsulating the integrated circuit package, a first integrated antenna structure for transmitting and/or receiving a first radio frequency signal, and a first array of electrically conductive vias extending through at least the first electrically isolating layer and the dielectric material. The first integrated antenna structure is arranged between the first and second electrically isolating layers and is surrounded by the electrically conductive vias which are electrically connected to respective first metal patches arranged on the dielectric material at the second side.

Abstract: A differential pressure sensor assembly includes a transducer having a first sensing surface and a second sensing surface. The second sensing surface is contained in a cavity. An Integrated Circuit (IC) is hermetically coupled to the transducer. The IC has a first aperture aligned to the cavity. A lead frame is coupled to the IC. The lead frame has a second aperture aligned to the first aperture of the IC. A package encapsulates the transducer, the IC and the lead frame. The package has a third aperture exposed to the first sensing surface. The package includes a molding compound providing a hermetic seal between the third aperture of the package and the first aperture of the IC. The molding compound is separated from the transducer by an encroachment distance.

Abstract: A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (TSV) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors. The via may be filled with an encapsulating material.

Abstract: Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed.

Abstract: The embodiments described herein provide microelectromechanical systems (MEMS) devices, such as three-axis MEMS devices that can sense acceleration in three orthogonal axes (e.g., x-axis, y-axis, and z-axis). In general, the embodiments described can provide decoupling between the sense motions of all three axes from each other. This decoupling is facilitated by the use of an inner frame, and an outer frame, and the use of rotative spring elements combined with translatory spring elements that have asymmetric stiffness. Specifically, the translatory spring elements facilitate translatory motion in two directions (e.g., the x-direction and y-direction) and have an asymmetric stiffness configured to compensate for an asymmetric mass used to sense in the third direction (e.g., the z-direction).

Abstract: A cell monitoring apparatus includes a processor and memory arranged to execute code representing a linear time-invariant state transition model and a non-linear observation model are provided to model a rechargeable cell using at least a non-linear open circuit voltage, an internal resistance, a time-invariant distortion voltage across a reactive component block, and a distortion current component constituting an error of measurement of current flowing through the reactive component block. An estimator unit performs extended Kalman filtering in respect of the state transition model and the observation model using the input state data in order to generate output state data. The processor is arranged to evaluate a criterion associated with at least part of the output state data and to generate a control signal in response to evaluation of the criterion.

Abstract: An interface system has a first media access controller having a first MAC buffer for storing at least one first-type frame in a first frame format according to a first communication protocol. A time synchronization module is arranged to, upon detecting the start of the first-type frame, determine a first timestamp from a master clock signal and latch the first timestamp into a first timestamp register. A processor is arranged to: retrieve the first timestamp from the first timestamp register, and transfer a first-type frame between the first MAC buffer and a first local memory in a block-wise manner as a plurality of blocks. The processor is arranged to process the plurality of blocks of the first-type frame using the first timestamp as retrieved from the first timestamp register.

Abstract: A method of implementing inter-component function calls. The method comprises generating a lower tier indirection data structure comprising an entry indicating a location in memory of a function within a first software component, a higher tier indirection data structure comprising an entry indicating a location in memory of the lower tier indirection data structure, and a configuration data structure comprising an entry defining an active version of the first software component. The method further comprises implementing executable computer program code for an inter-component function call by referencing entries within the configuration data structure, the higher tier indirection data structure and the lower tier indirection data structure.

Abstract: An equalizer for equalizing a composite signal originating from a given number of simultaneous data streams able to be received over a communication channel, on a given number of antennas, at one or more radio units, in a wireless communication system. The equalizer performs matrix operations when the number of receiving antennas associated with the composite signal is lower than the number of antennas supported by the equalizer. The channel matrix and the signal and interference covariance matrices are manipulated. The antenna dimension is increased, padding is then added and the transmitted signal vector is finally determined based on the altered matrices. A baseband processing unit, a method and a computer program are also claimed.

Abstract: A network receiver receives from a network an input signal which is sampled by a data sampler of the network receiver at sampling moments. Sampling moments have a relative position in time within a period of time of a single bit. The network receiver further includes a clock bit comparator and a sampling moment adaptor. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The sampling moment adaptor adapts the relative position of the sampling moment in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.

Abstract: A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

Abstract: An integrated circuit comprises a first functional unit and one or more other functional units. The first functional unit has an input for receiving data and an output for providing data. The integrated circuit tests and operates the first functional unit. Testing comprises: connecting the input of the first functional unit to the output of the first functional unit, thereby generating a loopback path from the output of the first functional unit to the input of the first functional unit; loading a test pattern onto the first functional unit; feeding a test clock signal comprising one or more clock edges, thereby prompting the first functional unit to transform the test pattern; and reading the transformed test pattern. Operating the first functional unit comprises: connecting the input of the first functional unit to an output of the other functional units; and feeding a normal clock signal to the first functional unit.

Abstract: A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme.

Abstract: An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.

Abstract: An electronic device has a runtime integrity checker for monitoring contents of storage locations in an address range. The runtime integrity checker has a location selector for selecting the storage locations by generating addresses within the address range for locations to be checked, an interface unit coupled to the location selector for receiving the addresses for accessing the locations to be checked via a bus interface, and a processor coupled to the interface unit for retrieving the contents from the locations to be checked. A mask unit is provided for processing a mask for defining the locations to be checked based on bits in the mask. The hardware enables selective monitoring of non contiguous storage locations or data areas.