Patents Assigned to Freescale
  • Integrated circuit with low power scan flip-flop
    Patent number: 9291674
    Abstract: A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sian Lu, Hao Wang
  • Synthesis of complex cells
    Patent number: 9293450
    Abstract: Hierarchical layout synthesis of complex cells. In some embodiments, a method may include partitioning a cell into a plurality of subcells, where the cell represents a set of electronic components in an integrated circuit; identifying, among the plurality of subcells, a most complex subcell; synthesizing a layout of the most complex subcell for each of one or more side-port configurations; selecting a side-port configuration based upon the layout of the most complex subcell; and synthesizing a layout of one or more of the plurality of subcells neighboring the most complex subcell by propagating one or more constraints associated with the selected side-port configuration.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Robert L. Maziasz
  • System for partitioning integrated circuit design based on timing slack
    Patent number: 9292651
    Abstract: A method of physical design of an IC using an EDA tool includes identifying elements of the IC design that have excess positive timing slack. The excess timing slack elements are placed in a separate partition and then parameters of the characteristics of the excess timing slack elements are modified to reduce their excess timing slack, such as reducing the voltage supplied to the separate partition, thereby lowering power consumption of the IC design.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chetan Verma, Amit Kumar Dey, Ashis Maitra, Kulbhushan Misri, Amit Roy, Harkaran Singh, Vijay Tayal
  • Lead frame with mold lock structure
    Patent number: 9293395
    Abstract: A lead frame for a semiconductor device includes a die paddle and leads situated on a perimeter of the lead frame. The die paddle has a metal frame and a number of substantially linear metal connecting bars within the frame. The connecting bars interconnect different locations of the frame to form a multiple triangles, where a triangular-shaped cavity is formed within each triangle. An overall area of the cavities is greater than an overall area of the connecting bars.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Wai Keong Wong, Soo Choong Chee, Stanley Job Doraisamy
  • Viterbi decoding device and method for decoding a signal produced by a convolutional encoder
    Patent number: 9294134
    Abstract: A Viterbi decoding device to decode a signal produced by a convolutional encoder is described. The device may include: an analog-to-digital conversion unit to extract a soft symbol S=(S0, S1) from the signal, the soft symbol including a first sample value S0 and a second sample value S1; and a digital processing unit to compute, for each of the N states, a branch metric value of BM—0_K in dependence on the soft symbol S, K being an index identifying the respective state. The digital processing unit may store the soft symbol S as a complex number S=S0+J*S1 in a complex number format; and compute a complex branch metric value BM—0_(K, K?)=BM—0_K+J*BM—0_K? in a complex number format on the basis of the soft symbol S, with K different from K?.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mihai-Ionut Stanciu, Ioan-Virgil Dragomir, Khurram Waheed
  • Reducing MEMS stiction by deposition of nanoclusters
    Patent number: 9290380
    Abstract: A mechanism for reducing stiction in a MEMS device by decreasing surface area between two surfaces that can come into close contact is provided. Reduction in contact surface area is achieved by increasing surface roughness of one or both of the surfaces. The increased roughness is provided by forming a micro-masking layer on a sacrificial layer used in formation of the MEMS device, and then etching the surface of the sacrificial layer. The micro-masking layer can be formed using nanoclusters. When a next portion of the MEMS device is formed on the sacrificial layer, this portion will take on the roughness characteristics imparted on the sacrificial layer by the etch process. The rougher surface decreases the surface area available for contact in the MEMS device and, in turn, decreases the area through which stiction can be imparted.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: March 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Ruben B. Montez
  • Data cache prefetch controller
    Patent number: 9292447
    Abstract: A processor includes a processing unit, a memory, a data cache, an One Block Look-ahead (OBL) prefetch engine, a Stride-Allocate on Miss (AoM) prefetch engine and a prefetch back-off module. The prefetch back-off module assigns and sets a status bits to a prefetched cache line and resets the status bit when the cache line is used by the processing unit. The back-off module also decrements a count value when at least two cache lines are used consecutively by the processing unit, increments the count value when at least two unused cache lines are evicted consecutively from the data cache, and disables cache line prefetching when the count value is greater than zero. The stride-AoM prefetch engine includes a reference pattern table (RPT) that stores details of only those instructions that have undergone a cache miss.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sourav Roy, Vikas Ahuja, Shourjo Banerjee
  • Hybrid synchronous/asynchronous counter
    Patent number: 9294099
    Abstract: A hybrid counter generates a multi-bit hybrid counter value. The hybrid counter includes two or more asynchronous counters, each configured to generate a subset of the bits of the multi-bit hybrid counter value. The asynchronous counters are interconnected by a logic gate and a clock gating circuit. The logic gate generates an asynchronous logic value based on the bits generated by the previous asynchronous counters. The clock gating circuit re-times the asynchronous logic value to generate a synchronous logic value that is used to toggle the next asynchronous counter. The hybrid counter functions more accurately than conventional asynchronous counters and with less power than conventional synchronous counters.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Rohit Goyal, Deepak Kumar Behera, Naman Gupta
  • Power MOSFET current sense structure and method
    Patent number: 9293535
    Abstract: A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Peilin Wang, Jingjing Chen, Edouard D. de Fresart, Pon Sung Ku, Wenyi Li, Ganming Qin
  • Error pad for safety device
    Patent number: 9292372
    Abstract: A safety device with an error indication function includes at least one ERROR pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the ERROR pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. The error indication block includes a fault collection and control unit for collecting and providing error occurrence information to the ERROR pad, and an ERROR pad select control register for storing ERROR pad selection and configuration information to control select inputs of the first set of multiplexers and provide the ERROR pad configuration information to the ERROR pad.
    Type: Grant
    Filed: May 18, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chandan Gupta, Neha Bagri, Ray C. Marshall
  • System and method for breakdown protection for switching output driver
    Patent number: 9294081
    Abstract: An integrated circuit device includes a driver circuit (100) having a pull-up network with a first pull-up transistor (108) coupled to a second pull-up transistor (110) at a first node (VP), and a pull-down network coupled to the pull-up network including a first pull-down transistor (112) coupled to a second pull-down transistor (114) at a second node (VN). A first bias switch (116) is coupled to the first node. A second bias switch (118) is coupled to the second node. A control circuit (104) is coupled to operate the first and second bias switches. The first bias switch is operated to reduce a voltage at the first node during a pull-down cycle of the driver circuit and the second bias switch is operated to reduce a voltage at the second node during a pull-up cycle of the driver circuit.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chang Joon Park, Charles E. Seaberg
  • Embedded data and code non-volatile memory cell configurations
    Patent number: 9293207
    Abstract: An integrated circuit including data and code non-volatile memory configuration is provided. The integrated circuit comprises a first non-volatile memory array for storing code and a second non-volatile memory array for storing data. The first non-volatile memory array comprises a plurality of first non-volatile memory cells, the first non-volatile memory cells each having a first channel width. The second non-volatile memory array comprises a plurality of second non-volatile memory cells, the second non-volatile memory cells each having a second channel width. The second channel width of the second non-volatile memory cells is larger than the first channel width of the first non-volatile memory cells. This allows the data non-volatile memory cells to have a higher transconductance than the code non-volatile memory cells.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Craig T. Swift
  • Memory access scheme for system on chip
    Patent number: 9292380
    Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.
    Type: Grant
    Filed: April 6, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR,INC.
    Inventors: Nitin Singh, Gaurav Jain, Amit Jindal, Rohit Tomar
  • Integrated circuit electrical protection device
    Patent number: 9293451
    Abstract: An integrated circuit electrical protection device includes a semiconductor substrate, and first, second, and third doped regions of a first polarity in the semiconductor substrate. The first and second doped regions are separated from one another by a first body region having a second polarity and the second and third doped regions are separated from one another by a second body region having the second polarity. The first and second polarities are different from one another. A fourth doped region of the second polarity directly abutting and in contact with the third doped region. A first gate structure is formed over the first body region between the first and second doped regions. A second gate structure is formed over the second body region between the second and third doped regions.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Michael A. Stockinger
  • System and method for data synchronization across digital device interfaces
    Patent number: 9292456
    Abstract: A system for synchronizing and re-ordering data transmitted between first and second clock domains associated with first and second device interfaces, respectively, includes a splitter, an arbiter, a transaction manager, and a read data buffer. The splitter receives a parent read request from one or more data input ports of the first device interface and splits it into one or more read requests. The arbiter receives the one or more read requests and selects one of the read requests and transmits it to the transaction manager. The transaction manager allocates an entry to the read request and then the read request is transmitted to the read data buffer. Thereafter, the read data buffer transmits the read request to the second device interface and transmits received response data to the first device interface.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Vinay Gupta, Nir Baruch, Amit Gur
  • Pressure sensor with differential capacitive output
    Patent number: 9290067
    Abstract: A MEMS pressure sensor device is provided that can provide both a linear output with regard to external pressure, and a differential capacitance output so as to improve the signal amplitude level. These benefits are provided through use of a rotating proof mass that generates capacitive output from electrodes configured at both ends of the rotating proof mass. Sensor output can then be generated using a difference between the capacitances generated from the ends of the rotating proof mass. An additional benefit of such a configuration is that the differential capacitance output changes in a more linear fashion with respect to external pressure changes than does a capacitive output from traditional MEMS pressure sensors.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Andrew C. McNeil, Yizhen Lin
  • System and method for dynamically managed task switch lookahead
    Patent number: 9292346
    Abstract: A processing system includes a processor pipeline, a detector circuit, and a task scheduler. The detector circuit includes a basic block detector circuit to determine that the processor pipeline received a first instruction of a first instance of a basic block, and to determine that a last-in-order instruction of the first instance of the basic block is a resource switch instruction (RSWI), and an indicator circuit to provide an indication in response to determining that the processor pipeline received the first instruction of a second instance of the basic block. The task scheduler initiates a resource switch, in response to the indication, at a time subsequent to the first instruction being received that is based on a cycle count that indicates a first number of processor cycles between receiving the first instruction and receiving the RSWI.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 22, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: James C. Holt, Brian C. Kahne, William C. Moyer
  • DEVICE HAVING A SECURITY MODULE
    Publication number: 20160078253
    Abstract: A device securely accesses data in a memory via an addressing unit which provides a memory interface for interfacing to a memory, a core interface for interfacing to a core processor and a first and second security interface. The device includes a security processor HSM for performing at least one security operation on the data and a remapping unit MMAP. The remapping unit enables the security processor to be accessed by the core processor via the first security interface and to access the memory device via the second security interface according to a remapping structure for making accessible processed data based on memory data. The device provides a clear view on encrypted memory data without requiring system memory for storing the clear data.
    Type: Application
    Filed: April 30, 2013
    Publication date: March 17, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Juergen FRANK, Michael STAUDENMAIER, Manfred THANNER
  • VOLTAGE REGULATION SYSTEM FOR INTEGRATED CIRCUIT
    Publication number: 20160077533
    Abstract: An integrated circuit (IC) includes a power grid having first, second, third, and fourth nodes for receiving first supply, first ground, second supply, and second ground voltage signals, respectively. A feedback circuit is connected to the second and fourth nodes for receiving the second supply and second ground voltage signals and generating a feedback voltage signal based on a difference between the second supply and second ground voltage signals. A resistor-ladder network receives the feedback signal and generates a sense voltage signal. A voltage regulator compares the sense voltage signal with a reference voltage signal and regulates the first supply voltage signal at a first voltage level.
    Type: Application
    Filed: September 16, 2014
    Publication date: March 17, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventor: Nishant Singh Thakur
  • RECEIVER SYSTEM AND METHOD FOR RECEIVER TESTING
    Publication number: 20160077196
    Abstract: A receiver system which may be implemented in an integrated circuit device and suitable for use in automotive radar systems such as collision avoidance systems, includes self test circuitry whereby a local oscillator test signal is generated by an on-board frequency multiplier and mixed in a down-conversion mixer with an RF test signal. The RF test signal is generated on the device by up-conversion of an externally generated low-frequency test signal with the local oscillator test signal. Baseband components may also be checked using test signals of suitable frequency divided down from the local oscillator test signal by a programmable frequency divider. This self test arrangement obviates any need for applying externally generated RF test signals to the IC device.
    Type: Application
    Filed: May 29, 2013
    Publication date: March 17, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Bernhard DEHLINK, Akbar GHAZINOUR, Ralf REUTER