Abstract: An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.

Abstract: An apparatus and corresponding method are provided to control a switched current circuit by switching the switched current circuit into an ON-state, waiting an amount of waiting an amount of time tB after the current within the switched current circuit increases above a current threshold, and switching the switched current circuit into an OFF-state after waiting the time tB. Further, a duration of time tA1 between switching the switched current circuit in the OFF-state and the point at which the current within the switched current circuit decreases below the current threshold is determined, and the method includes waiting a time tA2 after the current within the switched current circuit decreased below the current threshold, the time tA2 based at least in part on the time tA1, after which the switched current circuit is switched into the ON-state.

Abstract: A low drop-out voltage regulator, an integrated circuit, a sensor and a method of providing a regulated voltage are provided. The low drop-out voltage regulator comprises a regulated voltage driver for providing the regulated voltage in response to a control voltage, a feedback-loop circuit for generating the control signal such that the regulated voltage driving circuit provides the regulated voltage, and a pull-up circuit for pulling up the regulated voltage to a supply voltage when a difference between the supply voltage and the control voltage is smaller than a predetermined threshold value. In the feedback-loop circuit a first feedback voltage or a second feedback voltage is generated, respectively, on basis of a first ratio and a second ratio between the feedback voltage and the regulated voltage. The second feedback voltage is generated instead of the first feedback voltage when the regulated voltage is pulled-up to the supply voltage.

Abstract: A network receiver for a network using distributed clock synchronization and a method of adjusting a frequency of an internal clock of the network receiver are provided. The network receiver receives from the network an input signal and has an internal clock for generating a clock signal. The network receiver further includes a clock bit comparator and an adjustment signal generator. The clock bit comparator compares lengths of a first time period lapsed while receiving at least five consecutive bits of the signal and of an internal clock time interval representing the same number of bits as a number of bits of the first time period. The adjustment signal generator generates a frequency adjustment signal for controlling a frequency of the internal clock in dependence of a result of the comparison of the lengths to reduce a difference between the lengths.

Abstract: A microelectromechanical system (MEMS) sensor device includes a substrate, a support structure supported by the substrate, a membrane supported by the support structure and spaced from the substrate, and a polymer layer covering the membrane.

Abstract: The present application relates to a mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof. The mechanism is operative in an available state and a locked state. The mechanism comprises at least one context register and a bus interface for receiving a request. A filtering unit obtains information relating to a context of the received request. If in the available state, a managing unit loads the context register with the obtained context information; and grants access in response to the received request. If in the locked state, the managing unit detects whether the obtained context information matches with the context information stored in the context register; and if the obtained and stored context information match, grants access in response to the received request. Otherwise, access is denied.

Abstract: A memory array includes multiple memory cells, multiple bit lines, multiple word lines, and multiple source lines. Each memory cell includes a corresponding transistor and stores first and second data values. The transistor has corresponding first and second bit lines, and a source line for retrieving the first and second data values. The transistor has a gate terminal connected to a corresponding word line for receiving a word line enable signal, a first diffusion terminal connected to ground, and a second diffusion terminal connected to at least one of the corresponding first bit line, second bit line, and the source line for determining the first and second data values. The second diffusion terminal may be floating for determining the first and second data values.

Abstract: A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device.

Abstract: A method for fabricating an apparatus using radiation annealing includes forming an annealable layer on a substrate. A radiation absorbing layer is also formed on the substrate, wherein the radiation absorbing layer heats up In response to radiation, and the radiation absorbing layer is formed adjacent to at least a portion of the annealable layer and non-adjacent to a portion of the apparatus. Radiation is directed toward the apparatus to heat up the radiation absorbing layer to anneal the at least a portion of the annealable layer that is adjacent to the radiation absorbing layer without annealing the portion of the apparatus that is non-adjacent to the radiation absorbing layer.

Abstract: A system method of detecting address-swap faults in a multiport memory as described herein includes minimum testing for inversion faults and bit-swap faults for each port of the multiport memory. Different test types may be performed for inversion and bit-swap including pass/fail, and diagnostic testing for locating faulty ports. Pass/fail testing may be used for identifying whether the IC is good or bad, and additional diagnostic testing using additional cycles may be used for disabling faulty ports or correcting inverted address bits. The test method may be implemented as a function test or as a memory built-in self-test. The test method may be used during manufacturing test or during function design verification.

Abstract: A test structure includes two capacitor structures, wherein one of the capacitor structures has conductor plates spaced apart by a cavity, and the other capacitor structure does not include a cavity. Methodology entails forming the test structure and a pressure sensor on the same substrate using the same fabrication process techniques. Methodology for estimating the sensitivity of the pressure sensor includes detecting capacitances for each of the two capacitor structures and determining a ratio of the capacitances. A critical dimension of the cavity in one of the capacitor structures is estimated using the ratio, and the sensitivity of the pressure sensor is estimated using the critical dimension.

Abstract: ESD protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a first base well region having a first conductivity type, a collector region of the opposite conductivity type, and a second base well region having a dopant concentration greater than the first base well region, and a portion of the second base well region is disposed between the first base well region and the collector region. A third base well region with a different dopant concentration is disposed between the collector region and the second base well region. At least a portion of the first base well region is disposed between a base contact region and an emitter region within the second base well region.

Abstract: An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.

Abstract: Systems and methods for translating an oscillating electrical signal from a first impedance to an input impedance of a load include an adaptor that further includes at least one coaxial portion and an antenna portion. The at least one coaxial portion has a first end and a second end, and is configured to translate the oscillating electrical signal to the input impedance of the load. The antenna portion is coupled to the second end of the at least one coaxial portion and is disposed within the load. The antenna portion is configured to radiate electromagnetic signals corresponding to the oscillating electrical signal into the load.

Abstract: A method of processing a job is presented. A packet selector determines a candidate job list including an ordered listing of candidate jobs. Each candidate job in the ordered listing belongs to a communication stream. One or more shared resources required for execution of a first job in the candidate job list are identified. Whether the first job is eligible for execution is determined by determining an availability of the one or more shared resources required for the first job, and, when the one or more shared resource required for the first job are unavailable and no jobs executing within the data processor are from the same communication stream as the first job, determining that the first job is not eligible for execution.

Abstract: A supply voltage regulation system for an IC including a temperature sensor that detects temperature of the IC, a scaling resistor coupled between a power grid and a feedback node of the IC, a regulator amplifier that compares a voltage of the feedback node with a reference voltage for developing a supply voltage for the IC, and a temperature scaling circuit that drives a scaling current to the scaling resistor via the feedback node to adjust the supply voltage based on temperature. The temperature scaling circuit may include one or more comparators that compare a temperature signal with corresponding temperature thresholds for selectively applying one or more bias currents to the scaling resistor. The scaling resistor may be coupled to a hot point of the power grid. A voltage difference between a hot point of a ground grid may be converted to a bias current applied to the scaling resistor.

Abstract: A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted.

Abstract: Provided are a system and method for generating final result checking for a test case. A test case is executed for a coherent memory system having a processor core. An event log is generated for the processor core. The event log is analyzed. The test case for the core is annotated with a checker for performing expected data checking for physical addresses modified by the processor core.

Abstract: A MEMS pressure sensor (70) includes a sense cell (80), a test cell (82), and a seal structure (84). The test cell includes a test cavity (104), and the seal structure (84) is in communication with the test cavity, wherein the seal structure is configured to be breached to change an initial cavity pressure (51) within the test cavity (104) to ambient pressure (26). Calibration methodology (180) entails obtaining (184) a test signal (186) from the test cell prior to breaching the seal structure, and obtaining (194) another test signal (196) after the seal structure is breached. The test signals are used to calculate a sensitivity (200) of the test cell, the calculated sensitivity is used to estimate the sensitivity (204) of the sense cell, and the estimated sensitivity (204) can be used to calibrate the sense cell.

Abstract: A tester configured to test a strip of devices is provided. The tester may include a communications system, a plurality of communication lines, a plurality of multiplexors, each multiplexor having at least two outputs, wherein each multiplexor is configured to receive a signal generated by the communications system via one of the plurality of communication lines, and each multiplexor may be selectably coupled to at least two of the devices in the strip of devices. The tester may be configured to index the plurality of communication lines to a first subset of the devices, initiate at least one test, command the devices to generate data for each of the at least one tests, retrieve data from a first set of the devices, and retrieve data from a second set of the devices.