Abstract: A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.

Abstract: Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (NVM) device, are provided.

Abstract: A method for assembling a pressure sensor device uses a pressure-sensitive gel material that is applied to an active region of a pressure-sensing integrated circuit (IC) die. A molding compound is dispensed over the pressure-sensitive gel material to encapsulate the gel material. A portion of the molding compound is then removed to expose the gel material to an ambient environment outside of the packaged semiconductor device.

Abstract: A multi-port transmitter device for transmitting at least partly redundant data is described. The multi-port transmitter device comprises at least two transmitters comprising respective transmitter buffers. One transmitter is a master transmitter that issues a request to the processor to provide a data block when the transmitter buffer of the master transmitter has free space to store a data block. The processor is arranged to copy at least one data block of data stored in an external memory from the external memory to respective positions in a local buffer. The processor is arranged to, in accordance with a predefined sequence, sequentially initiate transfer of the data block from the respective position of the data block in the local buffer to the transmitter buffers of the at least two transmitters in response to a request from the master transmitter to provide a data block.

Abstract: A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

Abstract: A system for circuit for generating an output signal with a dynamically adjustable slew rate includes a sampler, an envelope detector, an envelope comparison and control circuit, and a voltage-driver circuit that includes output buffers for generating the output signal. The sampler generates a sampled signal indicative of the slew rate of the output signal. The envelope detector generates an envelope detection signal indicative of a peak value of the sampled signal. The envelope comparison and control circuit compares a voltage level of the envelope detection signal with various threshold voltage levels, and generates control signals. The voltage-driver circuit controls the operation states of the output buffers based on the control signals to dynamically adjust the slew rate of the output signal.

Abstract: A method of starting-up a switched reluctance, SR, motor is provided. The method comprises simultaneously energizing a plurality of phases at a first time point with respective phase voltages that are substantially the same, until the motor rotor is stabilized in alignment with either one of the plurality of phases; simultaneously de-energizing the plurality of phases at a second time point that follows the first time point; monitoring a decrease of respective phase currents in the plurality of phases from a third time point that follows the second time point by a first predetermined time interval; determining a phase of alignment of the rotor using evaluation of the decrease of the phase currents following simultaneous de-energizing of the plurality of phases; and, initiating rotation of the rotor from the determined phase of alignment of the rotor.

Abstract: A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

Abstract: A method for forming a pass-through layer of an interposer of a packaged semiconductor device in which conducting structures are extended between first and second ends of a casing. The conducting structures are subsequently encapsulated in a molding compound to form a molded bar, and the molded bar is sliced to obtain the pass-through layer. The pass-through layer has conducting vias, each corresponding to a sliced section of one of the conducting structures. The cost of pass-through layers formed in this manner may be less than that of comparable silicon or glass pass-through layers.

Abstract: A memory controller used to verify authenticity of data stored in a first memory unit. The memory controller includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. A processing system calculates a value which is representative of the data in the first memory unit after a write cycle. The calculation of the calculated value is triggered by the write cycle. The calculated value is compared with the pre-stored value in order to verify whether the data stored in the first memory unit after the write cycle has been altered in accordance with the authenticity. By comparing the calculated value with the pre-stored value authenticity of the data stored in the first memory unit after the write cycle is verified, thus preventing the memory controller from operating in case the data written to the first memory unit is not authentic.

Abstract: A display controller device for processing image data has a data processor for generating a display signal. The device has a writeback unit having an input coupled to the display signal and an output coupled to a debug interface. The writeback unit has a slice controller for defining a set of slices of the image and consecutively selecting slices of the set, and a slice selector for sampling pixel data from a selected slice. A slice buffer is coupled between the slice selector and the debug output for temporarily storing the selected pixel data. The slice controller transfers the selected pixel data to the debugger and subsequently selects a next slice until all slices of the set have been transferred. The debug system receives the slices and regenerates and displays the image.

Abstract: A radar device includes a RF signal source, two or more antenna interface units, a feed network, and a control unit. The RF signal source is arranged to provide a RF signal; each of the antenna interface units includes an antenna port and one of the following an amplifier and a mixer; the feed network includes two or more buffers, each buffer has an active and an inactive state; the control unit is arranged to generate or receive a selection signal which specifies none, one, or more of the antenna interface units as active antenna interface units and the remaining antenna interface units as inactive antenna interface units; the control unit is arranged to activate and deactivate the buffers in dependence on the selection signal so as to feed the RF signal to the none, one, or more active antenna interface units and not to the inactive antenna interface units.

Abstract: A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. A data input is arranged to repeatedly receive input data having a temporal input data resolution. A write controller is arranged to write newly received input data as received via the data input into the data storage memory. The writing comprises writing the newly received input data at the temporal input data resolution. The writing comprises keeping recent data at the temporal input data resolution in the data storage memory, and overwriting part of old data with newly received input data while keeping another part of the old data in the data storage memory at lower data resolution.

Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Abstract: A method for testing an integrated circuit design exercises the design using a set of simulation signals, and partitions a representation of the design into a first set of active elements and a second set of inactive elements. Only the active elements of the first set are exercised using a second set of simulation signals during verification of the integrated circuit design.

Abstract: A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface.

Abstract: Methods and systems are disclosed for frequency-domain symbol and frame synchronization for multi-carrier communication systems. Received signals are sampled and converted into frequency components associated with subcarriers within the multi-carrier communication signals. Symbol synchronization is performed in the frequency domain by performing correlation(s) between frequency components of the received signal and frequency-domain synchronization symbol(s). After symbol synchronization, frame synchronization correlation is also performed in the frequency domain between frequency components of the received signal and frequency-domain synchronization symbol(s). The disclosed embodiments are particularly useful for symbol and frame synchronization in multi-carrier received signals for power line communication (PLC) systems and/or other harsh noisy communication environments.

Abstract: A first storage location at a memory management unit stores physical address information mapping logical physical addresses to actual physical addresses. A second storage location stores an allowed address range of actual physical addresses. A memory management unit determines whether a write access to the first storage location is allowable. The access is to store memory mapping information relating to a first actual physical address. The memory management unit prevents the write access if the first actual physical address is not in the allowed address range, and does not prevent the write access if the first actual physical address is in the allowed address range. The memory management unit prevents a write access to the second storage location by a process that is not running in a hypervisor mode.

Abstract: A voltage converter such as a DC-DC buck regulator includes a driver circuit that enables charge stored on the parasitic capacitance of a transistor switch to be transferred to a load capacitor. Hence, stored charge can be harvested for use by a load, thereby increasing efficiency of the regulator.

Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.