Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.

Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

Abstract: The present invention provides a current source comprising a first bias current control element, the first bias current control element being configured to generate a first current if the control value is lower than a reference value and configured to generate a second current if the control value equal to or higher than the reference value. In addition or alternatively the bias current source comprises a second bias current control element, the second bias current control element being configured to generate a third current if the control value is lower than or equal to the reference value and configured to generate a fourth current if the control value is higher than the reference value. Furthermore, the present invention provides an integrated circuit and a method.

Abstract: A controller executes a first LBIST test on a device at a first shift frequency on a plurality of partitions and detects any voltage drop at sense points in each partition during the test. If a voltage drop is detected, then the test is re-run for those partitions that failed the first test. If failures are detected during the re-execution, then a further test at a lower shift frequency is performed. The partitions can be tested sequentially or in parallel and invention has the advantage of reducing the time taken for executing LBIST when the device is booted.

Abstract: A semiconductor memory device and method of operation are provided for a multi-bank memory array (100) with an address fault detector circuit (24, 28) connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (51-54) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a “no word line select,” “false word line select,” and “multiple word line select” failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (33-40) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.

Abstract: A semiconductor sensor device includes a device substrate, a micro-controller unit (MCU) die attached to the substrate, and a packaged pressure sensor having a sensor substrate and a pressure sensor die. The sensor substrate has a front side with the pressure sensor die attached to it, a back side, and an opening from the front side to the back side. A molding compound encapsulates the MCU die, the device substrate, and the packaged pressure sensor. A back side of the sensor substrate and the opening in the sensor substrate are exposed on an outer surface of the molding compound.

Abstract: A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.

Abstract: An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.

Abstract: An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.

Abstract: A MEMS device includes a first sense electrode and a first portion of a sense mass formed in a first structural layer, where the first sense electrode is fixedly coupled with the substrate and the first portion of the sense mass is suspended over the substrate. The MEMS device further includes a second sense electrode and a second portion of the sense mass formed in a second structural layer. The second sense electrode is spaced apart from the first portion of the sense mass in a direction perpendicular to a surface of the substrate, and the second portion of the sense mass is spaced apart from the first sense electrode in the same direction. A junction is formed between the first and second portions of the sense mass so that they are coupled together and move concurrently in response to an imposed force.

Abstract: A synchronous circuit comprises a functional circuitry and one or more validation circuits for validating synchronization of the functional circuitry. The functional and the validation circuits are clocked by a clock source. Each validation circuit comprises a clock distribution network, a test signal generator, a capture cell, a test signal path from the test signal generator to the capture cell, and a verification unit. The clock distribution network applies a launch clock signal at the test signal generator and a capture clock signal at the capture cell. The test signal generator produces a bi-level test signal. The test signal path transmits the test signal to the capture cell, which generates a proof sequence by sampling the test signal. The verification unit determines whether the proof sequence is identical to the test sequence. A method of designing a synchronous circuit and method of validating a synchronous circuit are also described.

Abstract: A digital up-converter (DUC) circuit for performing digital channel filtering of an incoming baseband digital signal. The proposed circuit reduces the complexity of the channel module filter of the DUC. This is achieved by taking advantage of the structure of the underlying symbol waveforms carried by the incoming baseband digital signal which have one or more known discontinuities comprising random amplitude and/or phase. Namely, the channel filter module is activated only for the digital samples located around the known discontinuities and is deactivated for the remaining digital samples. Further, the switching of the channel filter module from one state to another can be performed according to a smooth function so that further discontinuities are not introduced in the incoming baseband digital signal. A method and a computer program are also disclosed.

Abstract: A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type. An exception can be generated based upon the NaN of the different type being provided as a resultant.

Abstract: The present application suggests an electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal. The device comprises a random number generator to generate a random number signal varying in time which represents a divisor fraction signal; a signal mixer to mix the timely varying random number signal and a clock divisor signal and to output a mixed divisor signal; and a fractional clock divider to generate an output clock signal from a source clock signal, wherein the output clock signal has a frequency fout(t), which is substantially equal to the frequency fsource of the source clock signal being a narrow-band clock signal divided by a divisor D(t) represented by the mixed divisor signal.

Abstract: A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.

Abstract: A method and apparatus are described for fabricating a microchip structure (70) which protects interior electrical integrated circuits and components (120) attached to a lead frame die flag (104) using a molding compound (124) that mechanically interlocks with one or more positive mold lock structures formed as dummy wire loops (114) or stud bumps (214) that are attached to the lead frame (100) and/or die flag (104).

Abstract: A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad.

Abstract: A method for assembling a thin, flexible integrated circuit (IC) device includes using an etched contoured lead frame having raised features. A die is attached to the lead frame to form a sub-assembly that is then selectively coated with a low-modulus gel. The sub-assembly is covered with a temporary mask for sputter deposition of a metallic seed layer for interconnects between the die and the raised features. The mask is removed and more robust metal interconnects are grown over the seed paths using electroplating. The sub-assembly top is then coated with another gel layer. The bottom of the sub-assembly and of the contoured lead frame is removed, which transforms the raised features into leads. The newly exposed bottom of the sub-assembly is covered with a third layer of gel to complete assembly of the packaged device.

Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.

Abstract: A method of soft programming a non-volatile memory (NVM) array includes determining a first number based on a temperature of the NVM array and applying the first number of soft program pulses to a section of the NVM array. A first soft program verify of the section of the NVM array is then performed for a first time after completing the applying the first number of soft program pulses.