Abstract: A boost converter includes a comparator having first and second gain stages that operate in compare and auto-zero modes. The comparator measures voltage drop across a P-channel transistor to determine when current through an inductor reaches zero. When the inductor current reaches zero, the P-channel transistor becomes inactive to prevent a reduction in efficiency caused by allowing negative inductor current to draw current from a load. The comparator is then placed in a low power state. When the comparator is not in a compare mode, the comparator can operate in an auto-zero mode to cancel offset when measuring the input of the comparator.

Abstract: A level shifter operates using first and second input signals. When the first and second input signals are in respective first and second states, a first switching element is activated and an output node is pulled toward a first voltage, first pull-down protection and first pull-down switching elements are deactivated, a first protection node is connected to a first bias voltage, second pull-down protection and second pull-down switching elements are activated, and a second protection node is pulled to a second voltage. When the first and second input signals are in respective second and first states, the first switching element is deactivated, the first pull-down protection and first pull-down switching elements are activated, the output node and the first protection node are pulled toward the second voltage, the second pull-down protection and second pull-down switching elements are deactivated, and the second protection node is connected to the first bias voltage.

Abstract: An electrostatic discharge (ESD) protection circuit for protecting one or more devices in an electronic circuit from an ESD current which enters the electronic circuit through one or more input/output pins, the protection circuit comprising: a voltage clamp circuit connectable to the or each pin, for diverting the ESD current from the or each device; and a current sensor circuit connected between the input/output pins and the voltage clamp circuit and connected to the one or more devices, the current sensor circuit for sensing the ESD current and for switching off the or each device when the sensed current exceeds a threshold value, wherein when a current flows in the current mirror circuits above a threshold value the device is caused to switch off.

Abstract: A printed circuit board including a first outer layer, a second outer layer and an integrated circuit mounted on the second outer layer. The integrated circuit has a single exposed pad electrically connected to a ground reference, a first supply pin electrically connected to a first power supply and a second supply pin electrically connected to a second power supply, wherein the first power supply is configured to generate a first supply current with frequency components higher than the frequency components of a second supply current generated by the second power supply.

Abstract: A method of forming a semiconductor device includes forming a first conductive layer over the substrate. A dielectric layer, having a first opening, is formed over the first conductive layer. A seed layer is deposited over the first dielectric layer and in the first opening. A layer is formed of conductive nanotubes from the seed layer over the first dielectric layer and over the first opening. A second dielectric is formed over the layer of conductive nanotubes. An opening is formed in the second dielectric layer over the first opening. Conductive material is deposited in the second opening.

Abstract: A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.

Abstract: A sensor system includes a microelectromechanical systems (MEMS) sensor, processing circuitry, measurement circuitry, stimulus circuitry and memory. The system is configured to provide an output responsive to physical displacement within the MEMS sensor to the measurement circuitry. The stimulus circuitry is configured to provide a stimulus signal to the MEMS sensor to cause a physical displacement within the MEMS sensor. The measurement circuitry is configured to process the output from the MEMS sensor and provide it to the processing circuitry, which is configured to generate stimulus signals and provide them to the stimulus circuitry for provision to the MEMS sensor. Output from the measurement circuitry corresponding to the physical displacement occurring in the MEMS sensor is monitored and used to calculate MEMS sensor characteristics. Methods for monitoring and calibrating MEMS sensors are also provided.

Abstract: A demodulator suitable for demodulating binary FSK signals having a small difference between carrier frequencies uses a counter-timer technique for timing a fixed number FSK cycles and comparing a count value with a threshold when a frequency change is expected. By grouping a number of FSK pulses (or cycles) together in one measurement, speed requirements on the system clock used for the counter/timer measurements can be relaxed and tolerance to noise is also improved. The demodulator is particularly suitable for wireless charging applications.

Abstract: A device includes a power splitter configured to couple to an amplifier having a first path and a second path. The device includes a controller coupled to first and second variable attenuators and first and second adjustable phase shifters. The controller is configured to monitor a phase shift and an output power of each of the first path and second path of the amplifier, and adjust at least one of the first and second variable attenuators and the first and second adjustable phase shifters based upon the phase shift and the output power of each of the first path and second path of the amplifier to modify an input signal to the first path or the second path of the amplifier.

Abstract: A battery equalization circuit is provided, comprising: a positive battery node connected to a positive terminal of a monitored battery cell contained in a battery circuit that includes a plurality of other battery cells connected in series with the monitored battery cell; a negative battery node connected to a negative terminal of the monitored battery cell; a secondary transformer coil configured to receive a square wave, the secondary transformer coil having an upper transformer node and a lower transformer node; an upper switch connected between the positive battery node and the upper transformer node; a lower switch connected between the negative battery node and the lower transformer control node; and a control circuit configured to control operation of the upper and lower switches based on a measured cell voltage between the positive battery node and the negative battery node, and a total battery voltage of the battery circuit.

Abstract: A semiconductor device includes a semiconductor substrate, a body region disposed in the semiconductor substrate and having a first conductivity type, a source region disposed in the semiconductor substrate adjacent the body region and having a second conductivity type, a drain region disposed in the semiconductor substrate, having the second conductivity type, and spaced from the source region to define a conduction path, a gate structure supported by the semiconductor substrate, configured to control formation of a channel in the conduction path during operation, and having a side adjacent the source region that comprises a notch, the notch defining a notch area, and a notch region disposed in the semiconductor substrate in the notch area and having the first conductivity type.

Abstract: A voltage regulator comprises a ground node, a pick-off node, a regulator branch, a load branch, and a current mirror the regulator branch and the load branch are connected in parallel between the pick-off node and the ground node; the load branch comprises one or more resistive connecting lines that are connectable in series with the load to generate a load current through the load branch; the regulator branch comprises a bias node, a resistive element, and a tap node; the bias node is arranged to provide a regulated bias voltage; the resistive element is connected between the bias node and the pick-off node; and the tap node is connected between the bias node and the resistive element. The current mirror is connected to the tap node and arranged to draw a mirror current from the tap node; the mirror current having a component that is proportional to the load current.

Abstract: A circuit for driving a control gate of a split-gate nonvolatile memory cell may include a switched current source; a first transistor having a current electrode coupled to the switched current source and a control electrode coupled to a voltage source; a second transistor having a current electrode coupled to a second node of the switched current source, and a control electrode coupled to a third voltage source; a third transistor having a control electrode coupled to the second transistor, a current electrode coupled to the first transistor and a fourth switched voltage source; and a fourth transistor having a current electrode coupled to the first switched voltage source, a control electrode coupled to the switched current source, and a second current electrode coupled to the second transistor at a driver voltage node, wherein a voltage level at the driver voltage node is operable to drive the control gate.

Abstract: A monitoring device has an event monitor, an uplink interface to a chain controller device, and a downlink interface to a further monitoring device, and a daisy controller for coupling the uplink to the chain downlink. The event monitor, in response to detecting an event in sleep mode, generates a wake-up signal. The daisy controller sets the electronic monitoring device to a wake-up request mode and disables the bidirectional data communication via the downlink interface, and subsequently transmits a wake-up request to the chain controller device via the uplink interface. In response to receiving a wake-up command, the daisy controller re-enables the bidirectional data communication via the downlink interface and sets the electronic monitoring device to the operational mode. Thereby a wake-up sequence is performed while the wake-up request mode avoids bus conflicts.

Abstract: A method and apparatus for handling incoming data frames within a network interface controller. The network interface controller comprises at least one controller component operably coupled to at least one memory element. The at least one controller component is arranged to identify a next available buffer pointer from a pool of buffer pointers stored within a first area of memory within the at least one memory element, receive an indication that a start of a data frame has been received via a network interface, and allocate the identified next available buffer pointer to the data frame.

Abstract: Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

Abstract: An active I/Q generator circuit comprises an input node for receiving a reference oscillation signal. The circuit has an I-output and a Q-output for respectively outputting an I-signal and a Q-signal. A first active component is electrically coupled to the input node and arranged to amplify the reference oscillation signal and to output an amplified reference oscillation signal. A second active component is electrically coupled to the first active component to receive the amplified reference oscillation signal. The second active component is arranged to generate, based on the amplified reference oscillation signal, an in-phase signal and a, with respect to the in-phase signal, phase shifted signal, the second active component electrically coupled to the in-phase signal output for providing the in-phase signal and electrically coupled to the quadrature-phase output for providing the phase-shifted signal.

Abstract: A system for use in nodes communicating over a CPRI (common public radio interface) allows each networking node in a daisychain configuration to seamlessly manage the control and management HDLC (high-speed data link control) channel for both uplink and downlink. The connection is kept alive through a soft reset flow. Received HDLC packets can be extracted for use by a local node. Locally generated packets can be inserted into the packet data stream at the datalink layer for onward transmission over the CPRI. The system arbitrates between the locally generated packet data held in a buffer in the local node and remote packet data received from a remote node and held in the local node in a first in first out buffer for onward transmission to a subsequent node after arbitration. Remote packet data is given priority.

Abstract: A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode. A method of operating a processor is also disclosed.

Abstract: A configuration controller for and a method of controlling a configuration of a circuitry are provided. The configuration controller comprises an input, a selection checker, a data selector and an output. The input receives an input configuration selection signal which is encoded according to a specific encoding scheme. The selection checker checks a correctness of the received input configuration selection signal and provides to the data selector a selection signal which indicates a specific configuration selection if the input configuration selection data is correct or indicates a default configuration selection if the input configuration selection signal is incorrect according to the specific encoding scheme. The data selector selects configuration data from its internal configuration data storage in accordance with the selection signal and provides the selected configuration data to the output.