Abstract: A technique for frame synchronization in a communication system includes performing symbol correlation on received signal samples. A determination is made as to whether a magnitude of the symbol correlation is greater than a first threshold. In response to the magnitude of the symbol correlation being greater than the first threshold, an indication is provided that the received symbol is a valid symbol (e.g., a SYNCP symbol or SYNCM symbol). In response to the magnitude of the symbol correlation being less than the first threshold, an indication is provided that the received symbol is an indeterminate symbol (e.g., an invalid symbol or a SYNCM/2 symbol).

Abstract: A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.

Abstract: There is described a method of managing a flow of data packets in a multiple-processing entity system comprising a plurality of look-up tables adapted to store information associated to actions to be performed on packets received by the system. The method comprises storing, on a per entry basis, in a shadowed entry associated to any table entry being updated, the previous content of said table entry being updated, in association with a table entry version number, for use for managing packets received in the system prior to any update operation. It is thus possible to continue using look-up tables while updating process is being carried out for some or all of the table entries. The solution provides benefits for systems that are limited in space and cost, by use of minimal memory thanks to the storing of small shadowed data instead of full shadowed table.

Abstract: A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.

Abstract: A semiconductor device includes a single substrate including circuitry to implement a processor, a memory coupled to the processor, an audio interface module configured to provide data in pulse-code modulation (PCM) format having a first signal to noise ratio (SNR), and a medium quality speaker module configured to receive the PCM data, convert the data from the PCM format to a pulse-width modulation (PWM) format independently of the processor, and provide the data in the PWM format having a second SNR to at least one general purpose input-output pin on the substrate, the first SNR is greater than the second SNR.

Abstract: A no-lead type semiconductor package has a mold cap that forms a mold body. The corners of the mold body are reinforced with mold columns such that the corners have rounded protrusions and do not form 90° angles. The mold columns prevent the corner pads from peeling.

Abstract: A fractional frequency divider counts pulses of a digital input clock signal and enables a clock gating module when a preset count is reached. The clock gating module combines the outputs of two clock gating cells that receive, respectively, the input clock signal and an inverted version of the input clock signal. Output pulses are produced on both positive and negative edges of the input clock signal. This permits generation of output clock pulses that can be set to have a spacing and width granularity of half an input clock period, giving the advantages of low jitter and fine duty cycle control.

Abstract: A switch mode power supply has a first and second branch of an inductive element; a first switching element and a second switching element connected in series. Both branches are coupled to a power source in parallel. A controller controls said switching elements for operating said switch mode power supply in a plurality of consecutive time periods, wherein more than two of said switching elements are closed, i.e. at least one in each branch. The power supply has a polarity switching element coupled between said branches for receiving a pulsed voltage for providing an output voltage of a switchable polarity. The controller receives a feedback signal corresponding to the output voltage, compares the feedback signal to a reference waveform, and controls said switching elements and the polarity switching element in dependence of said comparing for generating the output voltage according to the reference waveform.

Abstract: Systems and methods are provided for delivering power from a first energy source to a second energy source. An electrical system for delivering power from a first energy source to a second energy source comprises an interface configured to be coupled to the second energy source, a switching element coupled between the first energy source and the interface, and a processing system coupled to the switching element and the interface. The processing system is configured to identify a connection event based on an electrical characteristic of the interface that is indicative of the interface being coupled to the second energy source and operate the switching element to provide a path for current from the first energy source in response to identifying the connection event.

Abstract: A relaxation oscillator shares charging current and comparator biasing current between just two current sources, thereby relaxing requirements on total supply current. The resulting reduction in power consumption has no adverse effect on the speed and accuracy of the oscillator. A switching arrangement directs charging and biasing currents between the two current sources and two charging capacitors and their associated comparators.

Abstract: A complementary push-pull buffer includes complementary transconductance (GM) devices connected as source-followers to drive a load. Current flowing through the GM devices is split, on the source side, between constant-current source circuitry and a push signal current multiplier (e.g., a current mirror) and, on the sink side, between constant-current sink circuitry and a pull signal current multiplier. The devices used to implement the constant-current circuits and the current multipliers are sized such that the current multipliers provide low output impedance, while the current splitting provides low overall power consumption.

Abstract: An AC-inverting amplifier for a waveform conversion circuit includes a first MOS transistor of a first conductivity type having a gate that receives an input signal, a drain that provides an inverted amplified output signal, and a source coupled to a first power supply voltage. A current source provides a first bias current and a second bias current in proportion to the first bias current. The second bias current is coupled to the drain of the first MOS transistor to bias the first MOS transistor. The first bias current has a magnitude that is determined by a DC voltage applied at the gate of the first MOS transistor.

Abstract: A clock doubler circuit includes a filtering circuit. The filtering circuit includes a first input to receive a first clock signal, a first output to provide a second clock signal, and a second output to provide a third clock signal. The third clock signal is a complementary signal to the second clock signal. The first clock signal, the second clock signal, and the third clock signal are at a first clock frequency. The second clock signal is a low pass filtered version of the first clock signal. The clock doubler circuit includes a frequency doubling circuit. The frequency doubling circuit includes a first input to receive the second clock signal and a second input to receive the third clock signal. The frequency doubling circuit includes an output node. The output node provides a fourth clock signal at a second clock frequency that is twice the first clock frequency.

Abstract: An electronic design automation (EDA) tool generates first and second instances, which are different in at least one aspect, of a cell representing a device, allowing a user to initiate an abutment of the first and second instances in a layout canvas, reads a position and orientation of each of the first and second instances to be abutted from the layout canvas, evaluates the respective positions and orientations of the first and second instances, altering a component of one of the first and second instances based on the evaluation, and then automatically abuts the first and second instances following the alteration of the component of the one of the first and second instances.

Abstract: An integrated circuit is provided that includes a plurality of modules comprising at least one clock-gated module and a controller unit, which is arranged to enable and disable provision of a clock signal to the at least one clock-gated module. The at least one clock-gated module includes one or more electronic circuits arranged to be in a first state of an electrical stress condition during a first portion of a period of time and in a second state of less electrical stress than in the first state during a second portion of the period of time. The at least one clock-gated module is further arranged to switch the one or more electronic circuits between the first state and the second state such that a change of a characteristic of at least one of the one or more electronic circuits caused by the electrical stress condition is at least partially reduced.

Abstract: A mechanism for recovering from stiction-related events in a MEMS device through application of a force orthogonal to the stiction force is provided. A small force applied orthogonal to the vector of a stiction force can release the stuck proof mass easier than a force parallel to the vector of the stiction force. Example embodiments provide a vertical parallel plate or comb-fingered lateral actuator to apply the orthogonal force. Alternate embodiments provide a proof mass of a second transducer to impact a stuck MEMS actuator to release stiction.

Abstract: A mechanism for express storage of sensor data in response to an indication of a power fluctuation, power brownout or blackout that can affect operation of a microcontroller is provided. Embodiments provide a flash memory having memory space allocated to express storage of the sensor data, and a protocol machine configured to provide the desired information to reserved registers associated with express program/erase operations accessing the allocated memory space.

Abstract: A reset generation circuit of an integrated circuit uses a scan data input pin as a scan mode exit control, which is enabled only when the IC reset pin of the device is active. The reset generation circuit allows a TAP controller to be scan testable yet at the same time the circuit provides a method to exit scan mode without requiring a power-up sequence or an extra pin.

Abstract: A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.

Abstract: A testing environment is provided in which both accelerometers and magnetometers can be tested in parallel, thereby decreasing the total cycle time for testing a semiconductor device package containing those devices. Embodiments of the present invention can also be configured to test singulated packages, thereby providing a tested and trimmed product that more accurately reflects the package delivered to the customer. In one embodiment, a series of device test locations within a testing region are configured to provide a known relationship with multiple fields of force. The device test locations are configured to provide sensitivity data from the packaged sensors in response to the directional forces. Embodiments provide a mechanism to transport the sensor packages from a device test location to a next device test location.