Abstract: An integrated circuit die includes a stack of a substrate and multiple layers extending in parallel to the substrate. A number of integrated electronic components is formed in the stack, and connected to form an electronic circuit. The electronic circuit comprises a first electric contact, a second electric contact, and a coupling which couples the electric strips electrically to each other. The coupling includes a circuit via which extends through at least two of the layers. The die further includes an integrated current sensor having a coil arrangement for sensing a current flowing through a part of the electronic circuit. The coil arrangement is magnetically coupled to the circuit via over at least a part of a length of the circuit via to sensing a magnetic flux through the circuit via. A measurement unit can measure a parameter of the coil arrangement representative of a current flowing through the circuit via.

Abstract: The present application relates an encoder and a method of operating thereof. The encoder is configured to partition an image domain into several substructures each having one of at least one size dimension; and to define at least one geometric primitive for each substructure on the basis of geometry data. The encoder is further configured, for each substructure, to retrieve a subset of image data and to determine whether pixel values of the retrieved subset are the same. If the pixel values are describable by a texture mapping operation the encoder is configured to define a compressed texture image and to assign texture mapping data to the geometry data. Otherwise the encoder is configured to define an uncompressed texture image and to assign texture mapping data to the geometry data. The compressed image comprises the geometry data, the texture mapping data and the texture image data.

Abstract: A transmission node in a wireless communication network includes a buffer, a transmitting section, a data processing section, a re-transmit queue, and a control section. To avoid duplication of SDUs for re-transmission, PDUs transformed from SDUs by the data processing section are maintained in the buffer by the control section after being transmitted to a mobile node in the network by the transmitting section. Addresses of the SDUs and associated sequence numbers are stored in the re-transmit queue. When handover of the mobile node from the transmission node to another transmission node occurs, PDUs of which the addresses are stored in the re-transmit queue are reverse transformed to SDUs with the associated sequence numbers so that the SDUs can be handed over to another transmission node.

Abstract: A circuit includes a non-volatile memory, a calibration circuit, and a sense amplifier. The sense amplifier senses a state of a memory cell during sensing. The sense amplifier includes a differential circuit having a first input coupled to a reference current source, a second input, and an output coupled to the calibration circuit during a calibration mode. A calibration current source is configured to be coupled to the second input of the differential current sensing circuit during the calibration mode and decoupled from the second input during the sensing mode. A variable current source is coupled to the differential current sensing circuit and the calibration circuit. The calibration circuit tests a plurality of currents of the variable current source during the calibration mode and selects one of the plurality of currents. The sense amplifier senses using the selected one of the plurality of currents.

Abstract: This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes.

Abstract: When data in first and second requests from a processor does not reside in cache memory, a first data element responsive to the second request is received by a cache controller from an external memory module after a first data element responsive to the first request and before the second data element responsive to the first request. Ownership of a linefill buffer is assigned to the first request when the first data element responsive to the first request is received. Ownership of the linefill buffer is re-assigned to the second request when the first data element responsive to the second request is received after the first data element responsive to the first request is received.

Abstract: A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first series circuit and a second series circuit in parallel with the first series circuit. The first series circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first adjustable attenuator series coupled between the first input and the first output. The second series circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter and a second adjustable attenuator series coupled between the second input and the second output.

Abstract: A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

Abstract: A memory includes a memory array, read circuitry, and a strobe generator. The read circuitry is configured to provide read data from the memory array in response to a read request, wherein the read circuitry provides the read data in accordance with a first clock. The strobe generator is configured to provide a strobe signal with the read data, wherein the strobe generator provides the strobe signal in accordance with a second clock. The second clock is out of phase with the first clock by a phase in a range of 30 degrees to 150 degrees.

Abstract: A method and apparatus for a radio base station (300) aligns IQ data blocks for transmission over multiple radio frequency (RF) signal paths (318, 328, 338) between a base station controller (304) and a plurality of antennas (340) at the base station by determining a path delay (317, 327, 337) for each RF signal path, and then transmitting IQ data blocks from JESD 204 transmit interfaces (301-303) over each RF signal path ahead of a first predetermined time slot by an advance time period equaling the path delay for each RF signal path, thereby aligning IQ data block signaling to the first predetermined time slot at the antennas.

Abstract: An embodiment of a packaged device includes first and second package leads, a first integrated circuit (IC) die, and a sub-assembly that includes a second IC die coupled to a substrate. The first IC die has a first coil, and the second IC die has a second coil. The first and second IC die are arranged within the device so that the first and second coils are aligned with each other across a gap between the first and second IC die, and the first and second IC die are galvanically isolated from each other. The first IC die is electrically coupled to the first package lead (e.g., with a wirebond), and a substrate bond pad is electrically coupled to the second package lead (e.g., with a wirebond). The sub-assembly also may include encapsulation at least over a wirebond that electrically couples the second IC die to the substrate.

Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.

Abstract: An integrated circuit package comprises a dielectric material, a first stack comprising at least a first electrically isolating layer and a second electrically isolating layer arranged at a first side of the integrated circuit package, an electrically conductive material arranged on a second side opposed to the first side, and an integrated antenna structure for transmitting and/or receiving a radio frequency signal arranged between the first and second electrically isolating layers. The electrically conductive material is separated from the integrated antenna structure by at least the dielectric material and the first electrically isolating layer, arranged to partly overlap the integrated antenna structure and to reflect the radio frequency signal received by the electrically conductive material through at least the first electrically isolating layer and the dielectric material to the first side.

Abstract: A communication system network element includes a Local Gateway co-located with a Home eNodeB. The Local Gateway has an open flow switch and a flow table, and provides service continuity of active SIPTO (selective IP traffic offload) sessions using open flow/software defined networking. An operator-controlled Open flow controller manages sessions at the Local Gateway. A flow modification feature is used to modify an existing flow in the flow table, which provides a means for interception and handover from a source Home eNodeB to a target Home eNodeB.

Abstract: An integrated circuit package comprises an electrically conductive material, a first electrically isolating layer having a first side in contact with the electrically conductive material and a second side opposite to the first side, a second electrically isolating layer stacked at the second side with at least the first electrically isolating layer and arranged at a package side, and an integrated antenna structure arranged between the first electrically isolating layer and the second electrically isolating layer. The electrically conductive material is encapsulated by a dielectric material, arranged to partly overlap the integrated antenna structure, separated from the integrated antenna structure by at least the first electrically isolating layer and arranged to reflect a radio frequency signal received by the electrically conductive material through at least the first electrically isolating layer to the package side.

Abstract: A data processing unit providing a core instruction set wherein the core instruction set comprises a specific core instruction that is adapted to receive data for specifying a hardware component to be called, call the hardware component for executing a job, perform a first context switch that suspends an actual task, wherein the actual task previously called the hardware component using the specific core instruction, perform a second context switch that resumes the actual task when the hardware component finished the job and a method for operating such a data processing unit.

Abstract: A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.

Abstract: A radio frequency coupling structure is arranged to couple a radio frequency signal between a first side of the radio frequency coupling structure to a second side of the radio frequency coupling structure opposite to the first side. The radio frequency coupling structure comprises a dielectric layer, a first electrically conductive layer comprising a first transition structure, a second electrically conductive layer comprising a second transition structure, and an integrated waveguide structure formed by an array of electrically conductive vias extending through the dielectric layer from the first to the second electrically conductive layer to enclose a portion of the dielectric layer. The portion is arranged to guide the radio frequency signal between the first transition structure and the second transition structure.

Abstract: A switching power converter for DC-DC converting has an inductance coupled between a power output and a high side switch in a controller device. The controller device has an error amplifier coupled to the power output and a reference voltage for activating the high side switch. The controller device has a bypass circuit including a bypass switch coupled between the supply input and the power output, a bypass driver having a first input coupled to the power output and a second input coupled to the reference voltage, and an output coupled to the bypass switch for activating the bypass switch. The controller further has a high bypass current sensor for generating a transient signal based on a current via the bypass switch, and a bandwidth control circuit for increasing the bandwidth of the error amplifier based on the transient signal.