Abstract: A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

Abstract: A system or circuit for generating timing events for mobile communications includes fetching network parameters corresponding to a transmission configuration. The network parameters are used to program a set of programmable registers. The timing events then are generated based on the network parameters. The timing events enable a user equipment (UE) or a base station to operate in various transmission configurations.

Abstract: A device simulation system performs a set of tests by applying, for each test in the set, a corresponding test stimulus to a simulation of the electronic device. In response to each test stimulus, the simulation generates corresponding output information which the device simulation system compares to a specified expected outcome to identify a test result for that test stimulus. In addition, for each test stimulus, the device simulation system generates test coverage information indicating the particular configuration of the simulated electronic device that resulted from the stimulus. The device simulation system correlates the coverage information with the test results to identify correlation rules that indicate potential relationships between test results and configurations of the simulated device.

Abstract: There is provided a multimedia computing apparatus for processing and displaying video data with overlay graphic data, said multimedia computing apparatus comprising a compression unit arranged to compress graphic overlay data prior to storage of said compressed overlay graphic data in a compressed display buffer, and a control unit arranged to determine when to compress the overlay graphic data dependent upon a refresh parameter of the overlay graphic data. There is also provided a method of adaptively compressing graphics data in a multimedia computing system comprising dynamically controlling compression of graphic overlay data in a display buffer dependent upon a refresh parameter of the graphic overlay data.

Abstract: An apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium are provided. The apparatus comprises an input for receiving an hierarchical integrated circuit design, a selector for selecting a candidate output pin, a cloner for adapting the hierarchical integrated circuit design, a re-connector for adapting the hierarchical integrated circuit design, and an output for outputting the adapted hierarchical circuit design. Optionally, the apparatus comprises a timing improver. The apparatus selects a candidate output pin of an IP block that is a node on at least two timing paths that have contradictory timing violations. The candidate output pin is cloned and at least one of the timings paths is connected to the cloned output pin for one of the instances of the IP block.

Abstract: The present disclosure presents a device and method for connecting an RF generator to a coaxial conductor. The device includes a substrate, a radio frequency generator on the substrate, and a coaxial conductor coupled to a first surface of the substrate. The coaxial conductor includes a conductive core and a conductive shield around the conductive core and is configured to transmit the radio frequency signal to a radiation device. The device includes a cap coupled to the substrate and extending from a second surface of the substrate opposite the first surface. The cap includes an outer wall and a center post. The outer wall is electrically connected to the conductive shield of the coaxial conductor and the center post is electrically connected to the conductive core of the coaxial conductor. An output pad of the radio frequency generator is electrically connected to the conductive core.

Abstract: An electronic device includes a set of two or more scan chains and a buffer chain. Each of the scan chains includes a sequence of stateful elements connected in series, and each of the scan chains is arranged to hold a string having a length identical to the length of the (50) respective scan chain. The strings of the scan chains are shifted in parallel from the scan chains into the memory unit and back from the memory unit into the respective scan chains. The store operation and the restore operation each include at least N0 elementary downstream shift operations. The set (100) of scan chains includes a short chain and a detour chain, wherein the short chain (C1) has a length N1 shorter than N0, and the buffer chain. The output end of the short chain is coupled to an input end of the (150) buffer chain. The buffer chain is provided at least partly by the detour chain.

Abstract: A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value.

Abstract: A method of fabricating a sensor device includes forming a plurality of sensor structures on a wafer, covering the plurality of sensor structures with a polymer layer, and dicing the wafer into a plurality of die while each sensor structure remains covered by the polymer layer.

Abstract: Adding a new subsystem node to a multi-node base station topology (e.g., a chain or tree topology) in a telecommunications network can disrupt the effective operation of the existing multi-node base station. By accurately measuring the timing difference between uplink and downlink signaling across a current terminating node during the configuration of the new terminating node, the new node can be added with reduced impact upon the operation of the existing base station nodes.

Abstract: An adjustable power splitter includes: a power divider with an input and a plurality, N, of divider outputs; a plurality, N, of adjustable phase shifters and a plurality, N, of adjustable attenuators series coupled to the divider outputs and providing a plurality, N, of power outputs; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the adjustable phase shifters and attenuation levels to be applied by the adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the adjustable phase shifters and the adjustable attenuators.

Abstract: An integrated circuit electrical protection device is disclosed that includes a semiconductor substrate and a plurality of transistor fingers partitioned into a plurality of segments. The segments are distinguished from one another by well-ties spaced apart from each other within a source/drain region that is shared by adjacent segments.

Abstract: A packaged semiconductor device has an integrated circuit (IC) die and first and second volumes of molding compound. The first volume of molding compound is disposed on a first portion of a first side of the IC die and comprises a first molding compound. The second volume of molding compound is disposed on a second side of the IC die, different from the first side, and comprises a second molding compound, different from the first molding compound. By including different molding compounds, the properties of the packaged semiconductor device can be varied across the device.

Abstract: A method of generating test patterns for testing a semiconductor processor for small delay defects (SDD) includes modifying interconnect delay values of interconnect paths by introducing values corresponding to (i) set-up and clock to Q delays of elements in the paths and (ii) latencies of associated clock networks. Critical nodes are selected and test patterns targeting the selected critical nodes are generated using timing slack resulting from the modified interconnect delays. A first selection of nodes that are critical in at-speed scan mode testing and a second selection of nodes that are critical in functional mode testing are made by static timing analysis (STA). Only the nodes featuring in both the first and second selections are selected for targeting small delay defects using at-speed scan test patterns.

Abstract: A processor implements a priority search tree on data elements. A data point having two component values is stored for each data element. A comparison is performed to determine an order for two data points. When the first component values of the two data points are equal, a comparison is made using the second component values. When the second component values of the two data points are equal, a comparison is made using the first component values.

Abstract: A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements.

Abstract: In some embodiments, a power supply slew rate detector may include a filter circuit having a capacitive element operably coupled to a power supply output provided to a flash memory circuit and a resistive element operably coupled to the capacitive element and to ground, and a Schmitt trigger including an input operably coupled to a node between the capacitive element and the resistive element, the Schmitt trigger further including an output configured to indicate a slew rate of the power supply output.

Abstract: Bipolar transistors and methods for fabricating bipolar transistors are provided. In one embodiment, the method includes the step or process of providing a substrate having therein a semiconductor base region of a first conductivity type and first doping density proximate an upper substrate surface. A multilevel collector structure of a second opposite conductivity type is formed in the base region. The multilevel collector includes a first collector part extending to a collector contact, a second collector part Ohmically coupled to the first collector part underlying the upper substrate surface by a first depth, a third collector part laterally spaced apart from the second collector part and underlying the upper substrate surface by a second depth and having a first vertical thickness, and a fourth collector part Ohmically coupling the second and third collector parts and having a second vertical thickness different than the first vertical thickness.

Abstract: A system-on-chip comprising a sender unit and a receiver unit and a method of operating thereof are described. The sender unit comprises a send counter for providing a send counter value. The receiver unit comprises a receive counter for providing a receive counter value. The sender unit is arranged to increment the send counter value by an increment and send a data packet to the receiver unit. The receiver unit is arranged to receive the data packet and increment the receive counter value by the increment. In a challenge operation, the sender unit sends the send counter value to the receiver unit. In a challenge response operation, the receiver unit receives the send counter value, compares the values, and generates a comparison result. Loss of data packets from the sender unit as well as reception of unexpected data packets from a third functional unit may thus be detected.

Abstract: A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.