Abstract: A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively.

Abstract: A pressure sensor device includes a gel retainer that is mounted or formed on a substrate. The gel retainer has a cavity and a pressure sensing die is mounted inside the cavity. The die is electrically connected to one or more other package elements. A pressure-sensitive gel material is dispensed into the cavity to cover an active region of the pressure sensing die. A mold compound is applied on an upper surface of the substrate outside of the gel retainer.

Abstract: A floating-point value can represent a number or something that is not a number (NaN). A floating-point value that is a NaN includes a portion that stores information about the source operands of the instruction.

Abstract: A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

Abstract: A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout.

Abstract: The embodiments described herein provide a radio frequency (RF) driver amplifier and method of operation. In general, the driver amplifier facilitates high performance operation in RF devices while being implemented with only n-type transistors. Using only n-type transistors in the driver amplifier can increase the operating bandwidth of the driver amplifier. Furthermore, using only n-type transistors in the driver amplifier can simplify device fabrication. The driver amplifiers and methods described herein can be used in a variety of applications. As one specific example the driver amplifier can be used in a switch-mode power amplifier (SMPA). Such a SMPA can be configured to amplify a time varying signal, such as an RF.

Abstract: A ground-loss detection circuit for an integrated circuit, (IC) device including a first dynamic threshold metal oxide semiconductor (DTMOS) device operably coupled between a first ground plane of the IC device and at least one further ground plane of the IC device, at least one of the first and at least one further ground planes comprising an external ground connection of the IC device, at least one further DTMOS device operably coupled between the first and at least one further ground planes of the IC device in an opposing manner to the first DTMOS device, and at least one ground-loss detection component operably coupled to at least one of the first and at least one further DTMOS devices and arranged to detect a ground-loss for at least one of the first and at least one further ground planes based at least partly on a drain current of the at least one of the first and at least one further DTMOS device(s).

Abstract: A integrated circuit device has at least one instruction processing module arranged for executing vector data processing upon receipt of a respective one of a set of data processing instructions. The data processing instructions include at least one matrix processing instruction for processing elements of a matrix. The elements of rows of the matrix are stored in a set of register, and the instruction processing module comprising an accessing unit for accessing selected elements of the matrix, which selected elements are non-sequentially located according to a predetermined pattern across multiple registers of the set of registers, the accessing enabling respective processing lanes to write or read different registers. Advantageously elements in columns of a matrix can efficiently be processed.

Abstract: A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory [NVM] comprising a plurality of NVM lines.

Abstract: A phase locked loop having a normal mode and a burn-in mode. The logic portion is coupled to a logic power supply terminal and includes a clock receiver coupled to a phase frequency detector. The analog portion has a charge pump coupled to the phase frequency detector and to an analog power supply terminal. The analog portion also has a voltage controlled oscillator coupled to the charge pump at an analog node and to the analog power supply terminal. The phase locked loop has a node control circuit that is coupled to the analog node during the burn-in mode that controls a voltage at the analog node sufficiently below a voltage at the analog power supply terminal to avoid over-stressing the charge pump and the voltage controlled oscillator during the burn-in mode.

Abstract: A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Abstract: Fabrication processes for semiconductor devices are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.

Abstract: A method and apparatus are provided for error correction of a memory by using a first memory (18) and second memory (14) to perform error correction code (ECC) processing on data retrieved from the first memory and to use status control bits (35-37) in the second memory to detect and manage hard and soft errors identified by the ECC processing.

Abstract: A device includes a Doherty amplifier having a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a variable impedance coupled to an output of the Doherty amplifier, and a controller configured to set the variable impedance to a first impedance when an output power level of the Doherty amplifier is less than a threshold and to a second impedance when the output power level of the Doherty amplifier is above the threshold.

Abstract: To facilitate dynamic lockstep support, replacement states and/or logic used to select particular cache lines for replacement with new allocations in accord with replacement algorithms or strategies may be enhanced to provide generally independent replacement contexts for use in respective lockstep and performance modes. In some cases, replacement logic that may be otherwise conventional in its selection of cache lines for new allocations in accord with a first-in, first-out (FIFO), round-robin, random, least recently used (LRU), pseudo LRU, or other replacement algorithm/strategy is at least partially replicated to provide lockstep and performance instances that respectively cover lockstep and performance partitions of a cache. In some cases, a unified instance of replacement logic may be reinitialized with appropriate states at (or coincident with) transitions between performance and lockstep modes of operation.

Abstract: An oscillator includes an amplifier and a piezoelectric crystal coupled across a portion of the amplifier. A low pass filter (LPF) passes the common-mode voltage component of the crystal output signal. An auxiliary bias circuit uses a shared LPF component to charge a crystal load capacitor during start-up of the oscillator, and to provide a DC bias operating point to the oscillator driver transistor. A buffer amplifier receives the common-mode voltage component on the non-inverting input. The buffer amplifier output is coupled to both the inverting input and the drain terminal of the oscillator driver transistor such that the gate and drain DC bias voltages of the oscillator driver transistor are substantially the same. An automatic loop control circuit receives the crystal output signal and the common-mode voltage signal, and generates a bias control signal to bias the amplifier and the auxiliary bias circuit.

Abstract: A method of forming a pillar bump includes feeding a bond wire in a capillary. The capillary has a hole portion and a chamfer section arranged downstream of the hole portion. The hole portion has a length along a feed direction of the bond wire that is greater than a maximum diameter of the hole portion. The method further includes performing an electric flame off (EFO) on a free end of the bond wire extending from the chamfer section to form a free air ball (FAB), tensioning the bond wire and applying a vacuum to the capillary to withdraw a portion of the FAB back into the capillary to substantially fill the hole portion for forming a tower, attaching the FAB to a bonding site, and at least partially removing the capillary from the bonding site and breaking the bond wire above the tower.

Abstract: A packaged semiconductor device is assembled using a first lead frame upon which a die is mounted and encapsulated and a second lead frame that provides bent leads for the device. By using two different lead frames, an array of the first lead frames can be configured with more lead frames for more devices than a comparably sized lead frame array of the prior art because the first lead frame array does not need to provide the leads for the packaged devices. Instead, the leads are provided by the second lead frame array, which can be attached to the first lead frame array after the dies have been mounted and encapsulated on the first lead frame array.

Abstract: An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.