Abstract: An electronic device has a calibration arrangement for controlling a frequency characteristic of a PLL circuit having a phase comparator having an output for generating a phase difference signal, a voltage controlled oscillator and a divider. The divisor of the divider is programmable, and the oscillator is also directly modulated by an oscillator modulation signal. A modulation unit has a modulation input for receiving a modulation signal and generates the oscillator modulation signal and the divisor such that modulation generates a predefined change of the output frequency and a change of the divisor proportional to said predefined change. The calibration arrangement receives the phase difference signal, and has a ripple detector for providing a detector output signal by detecting a ripple on the phase difference signal correlated to edges in the modulation signal. A calibration control unit adjusts the oscillator modulation signal based on the detector output signal such that the ripple is reduced.

Abstract: The invention relates to a Frequency Divider Circuit for dividing an input RF signal to a frequency divided RF signal. The circuit comprises a RF pair, a switching-quad pair coupled in series with a transimpedance amplifier and a double pair of emitter followers. The circuit comprises coupling elements for providing first DC paths to first amplifier paths of the RF pair and for providing second DC paths to second amplifier paths of the series arrangement of the switching-quad pair and the transimpedance amplifier. The first DC paths are independent of the second DC paths. RF connections are provided to couple the first and the second amplifier paths for transferring a signal from the first amplifier paths to the second amplifier paths.

Abstract: Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.

Abstract: A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.

Abstract: A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.

Abstract: A data processing device includes an interconnect controller operable to manage the communication of information between modules of the data processing device via an interconnect. In response to a transaction request the interconnect controller selects a tag value from a set of available tag values, assigns the tag to the transaction and reserves the tag value so that it is unavailable for assignment to other transactions. If an expected response to the transaction request is not received within a designated amount of time, the transaction enters a timed-out state and the interconnect controller locks the tag value, so that it remains unavailable for assignment to other transactions until an unlock event, such as a request from software.

Abstract: Systems and methods for releasing semiconductor dies from an adhesive tape or film. In some embodiments, a semiconductor manufacturing device may include: a chuck plate configured to support an array of semiconductor dies, where each die in the array has a top surface and a bottom surface, where each die's bottom surface is bonded to an adhesive tape, and where the chuck plate comprises one or more channels configured to apply a negative pressure to the adhesive tape; and a tape release element having an irregular surface, the tape release element disposed between the chuck plate and the adhesive tape.

Abstract: A semiconductor package has multiple dies and an interior power bar that extends within an interior space formed within the die flag between the dies. The bond pads located on the interior side of each die are wire-bonded to the interior power bar. Some embodiments may have more than two dies and/or more than one interior power bar between each pair of adjacent dies.

Abstract: A method for packaging an integrated circuit (IC) device in which conventional manufacturing steps of mechanically bonding a die to a corresponding interconnecting substrate, wire bonding the die, and encapsulating the die in a protective shell are replaced by a single manufacturing step that includes thermally treating an appropriate assembly of parts to both form proper electrical connections for the die in the resulting IC package and cause the molding compound(s) to encapsulate the die in a protective enclosure.

Abstract: A system (and a method) are disclosed for intelligently fetch one or multiple reference blocks from memory for each block to be motion compensated or motion estimated within a video processing system. The system includes a reference block configuration evaluation unit and a motion compensation memory fetching unit. The reference block configuration evaluation unit analyzes the reference block configuration of the block being motion compensated with a plurality of reference block configurations of its neighboring blocks. In response to a reference block configuration evaluation result, the reference block configuration evaluation unit decides the configuration of reference blocks to be fetched from a memory. The motion vector memory fetching unit fetches the number of reference blocks for motion compensation accordingly.

Abstract: A transmitter is provided that comprises an oscillator, a power amplifier, and a heating element. The power amplifier generates a high power signal according to the low power signal. The transmitter may be operated such that a heat production rate of the group consisting of the power amplifier and the heating element is substantially constant. The heating element may be a dummy power amplifier. A method of operating a transmitter is also disclosed.

Abstract: A voltage controlled oscillator (VCO) comprising a first supply node, a second supply node, an oscillation transistor, a biasing network, an output node and a feedback network is described. The VCO is be powered by a supply voltage applied across the first and second supply nodes. The oscillation transistor and the biasing network are connected in series between the first supply node and the second supply node. The output node is connected to the oscillation transistor so as to deliver an oscillatory output signal. The feedback network provides an oscillatory feedback signal from the output node to the biasing network. The feedback network comprises a capacitive element and a transmission line connected in series for transferring the feedback signal. The VCO may be integrated in a radar device, for example.

Abstract: An integrated circuit device comprises a first integrated circuit and a second integrated circuit wherein the first and second integrated circuits are comprised on a single semiconductor die. The second integrated circuit is a safety circuit arranged to monitor the operation of the first integrated circuit, report any detected faults and drive the device into a failsafe state if a fault is detected. The first integrated circuit may be a power management module for a safety critical system. An isolation barrier in the form of a trench is formed between the two integrated circuits so that the safety circuit is protected from any high voltage or thermal stresses arising in the first integrated circuit. The device has particular application to automotive safety-critical systems such as electric power steering systems.

Abstract: A method of managing a thermal budget, for at least a part of a processing system, is described. The method comprises, upon detection of a use case event, determining a thermal budget violation time window for a current use case scenario of the at least part of the processing system, and managing the thermal budget for the at least part of the processing system based at least partly on the determined thermal budget violation time window.

Abstract: A system for providing a first voltage generated by a main supply and a second voltage generated by a battery to an integrated circuit (IC) includes supply-selection, control logic and switching circuits. The supply-selection circuit includes first, second, and third transistors. The switching circuit includes fourth and fifth transistors that supply the first and second voltages to the IC when switched on. The supply-selection circuit selects and provides the higher of the first and second voltages to body terminals of the fourth and fifth transistors for maintaining required body-bias voltage conditions. The control logic circuit generates a first control signal as long as the first voltage is within a predetermined range for keeping the fourth transistor switched on and a second control signal when the first voltage is not within the predetermined range for switching on the fifth transistor to supply the second voltage.

Abstract: Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. The magnetometer wafer is bonded to the accelerometer wafer to produce a bonded wafer stack. The bonded wafer stack is then singulated to yield a plurality of multi-sensor microelectronic packages each including a singulated magnetometer die bonded to a singulated accelerometer die.

Abstract: A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.

Abstract: An RF power amplifier circuit has an input terminal for receiving an input signal having an input power, and an output terminal for outputting an output signal. The RF power amplifier circuit comprises three amplifier stages and an input power splitter for providing respective power fraction signals to respective inputs of each amplifier stage. The input power splitter comprises a first input transmission line arranged between a first node and a second node, a second input transmission line arranged between a third node and a fourth node, and an electrical reactive element having a first terminal electrically connected to both the first and the second nodes, and a second terminal electrically coupled to a third one of the respective three inputs.

Abstract: A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal.

Abstract: A safety device with an error indication function includes at least one ERROR pad configured between the error indication function and at least one normal function, and a set of multiplexers connected to the ERROR pad. The safety device further includes an error indication block and a functional block multiplexed by the set of multiplexers. The error indication block includes a fault collection and control unit for collecting and providing error occurrence information to the ERROR pad, and an ERROR pad select control register for storing ERROR pad selection and configuration information to control select inputs of the first set of multiplexers and provide the ERROR pad configuration information to the ERROR pad.