Abstract: A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal.

Abstract: Methods for fabricating multi-sensor microelectronic packages and multi-sensor microelectronic packages are provided. In one embodiment, the method includes positioning a magnetometer wafer comprised of an array of non-singulated magnetometer die over an accelerometer wafer comprised of an array of non-singulated accelerometer die. The magnetometer wafer is bonded to the accelerometer wafer to produce a bonded wafer stack. The bonded wafer stack is then singulated to yield a plurality of multi-sensor microelectronic packages each including a singulated magnetometer die bonded to a singulated accelerometer die.

Abstract: An RF power amplifier circuit has an input terminal for receiving an input signal having an input power, and an output terminal for outputting an output signal. The RF power amplifier circuit comprises three amplifier stages and an input power splitter for providing respective power fraction signals to respective inputs of each amplifier stage. The input power splitter comprises a first input transmission line arranged between a first node and a second node, a second input transmission line arranged between a third node and a fourth node, and an electrical reactive element having a first terminal electrically connected to both the first and the second nodes, and a second terminal electrically coupled to a third one of the respective three inputs.

Abstract: Processing logic circuit for use in a computing system has State Retention Power Gating logic circuit including at least two scan chains having different lengths and operable to collect state information about at least a portion of the processing logic circuit before the at least a portion of the processing logic circuit is placed from a first state into a second, different, state. The processing logic circuit includes a memory operable to store collected state information about the at least a portion of the processing logic circuit, and logic circuit operable to rearrange the collected state information data for scan chains shorter than a longest scan chain within the at least a portion of the processing logic circuit, to enable valid return of the collected state information data, for the scan chains shorter than a longest scan chain, to the at least a portion of the processing logic circuit when the at least a portion of the processing logic circuit returns to the first state.

Abstract: A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.

Abstract: A quad flat package integrated circuit (IC) device has alternating inner and outer leads that protrude from a package body. The inner leads are j-shaped leads and the outer leads are gull-wing shaped leads. The package body is formed such that it includes plastic lead webbings between adjacent leads, which help prevent metal particles from getting lodged between the leads and causing electrical shorts. The webbings are made of the same molding compound as the package body and are formed together with the package body.

Abstract: Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.

Abstract: A latching level shifter coupled to a first power supply voltage is driven by a logic circuit coupled to a second power supply voltage. The latching level shifter is driven in a first mode to store a state based on an input signal received by the logic circuit, the first and second power supply voltages are set at first and second initial voltage levels. The latching level shifter is driven in a second mode subsequent to the first mode, the first power supply voltage is set to an intermediate voltage level. The latching level shifter is driven in a high voltage protection mode to produce an output voltage based on the state, the first power supply voltage is set to a final voltage level that is greater than a final voltage level of the second power supply voltage. The high voltage protection mode is subsequent to the second mode.

Abstract: A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal.

Abstract: A method for applying a pressure-sensitive gel material during assembly of an array of pre-singulated packaged semiconductor devices. In the method, pressure-sensitive gel material is dispensed onto a first semiconductor device of the array, where the first semiconductor device is disposed within a first cavity. A first curing process is performed to partially cure the pressure-sensitive gel material in the first cavity. Pressure-sensitive gel material is then dispensed onto another semiconductor device of the array, where the other semiconductor device is disposed within another cavity. The first curing process is initiated before the dispensing of the pressure-sensitive gel material inside of the other cavity is completed and initially cures pressure-sensitive gel material for fewer than all of the pre-singulated packaged semiconductor devices of the array.

Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

Abstract: A MEMS device (20) includes a movable element (20) suspended above a substrate (22) by a spring member (34) having a spring constant (104). A spring softening voltage (58) is applied to electrodes (24, 26) facing the movable element (20) during a powered mode (100) to decrease the stiffness of the spring member (34) and thereby increase the sensitivity of the movable element (32) to an input stimulus (46). Upon detection of a stiction condition (112), the spring softening voltage (58) is effectively removed to enable recovery of the movable element (32) from the stiction condition (112). A higher mechanical spring constant (104) yields a stiffer spring (34) having a larger restoring force (122) in the unpowered mode (96) in order to enable recovery from the stiction condition (112). A feedback voltage (56) can be applied to feedback electrodes (28, 30) facing the movable element (32) to provide electrical damping.

Abstract: Power control circuitry for a data processor supplies a memory array with a supply voltage corresponding to a memory performance level. The performance levels include a full performance level and a power-saving performance level. Voltage sensing circuitry senses a voltage level of the memory array and outputs a power status signal. The power status signal is used to determine when the memory array is awake and can be accessed.

Abstract: An electromagnetic band gap device is provided, comprising: a conductive plane; a non-conductive substrate located over the conductive plane; and an electromagnetic band gap unit cell that includes a first via located in the non-conductive substrate and filled with a conductive material, a second via located in the non-conductive substrate and filled with the conductive material, a first conductive surface located on the non-conductive substrate over the first via, and a second conductive surface located on the non-conductive substrate over the second via, wherein the electromagnetic band gap unit cell is configured to operate as an LC resonant circuit in conjunction with the conductive plane, at least one gap is located in the electromagnetic band gap unit cell, the at least one gap being located in the first via, in the first conductive surface, in the second conductive surface, and in the second via.

Abstract: A power management system permits a small microcontroller subsystem or low power domain to continuously operate while a main subsystem domain is cycling from power on to off. The power management system supports asynchronous domains with common shared peripherals. The asynchronous domains operate as a single entity while in a full power mode with the peripheral and system resources being shared. The system can be used in automotive systems where most of the system is power-gated leaving just a power regulator controller, some counters and an input/output segment alive for wakeup purposes.

Abstract: A power management system for an integrated circuit (IC) includes low and full-power bandgap generators, first and second multiplexers, first circuitry, and a full-power regulator. When the IC is powered on, the first multiplexer selects the full-power bandgap generator as a reference voltage source for the first circuitry. After the low-power bandgap generator has been trimmed, the first multiplexer selects the low-power bandgap generator as the reference voltage source for the first circuitry. When the IC transitions from low power mode to high power mode, the second multiplexer selects the low-power bandgap generator as the reference voltage source for the full-power regulator. When the full-power bandgap generator is powered on, the second multiplexer selects the full-power bandgap generator as the reference voltage source for the full-power regulator.

Abstract: A semiconductor chip package includes a lead frame having a die paddle, leads surrounding the paddle and a central window through the paddle. A substrate has a base side and a superior side. A peripheral portion of the base side is secured to the paddle and a central portion of the base side is exposed through the central window. A semiconductor chip is secured to the superior side of the substrate. The semiconductor chip is electrically connected to the plurality of leads and the substrate. A mold compound covers at least portions of the lead frame, the substrate and the semiconductor chip. The chip package can be electrically connected to other devices or a circuit board by way of the leads and BGA pads of the substrate exposed in the central window.

Abstract: A semiconductor device includes a lead frame having a flag and leads that surround the flag. The leads include a dummy lead that has first and second wire bonding areas. A first die is attached on the flag and electrically connected to the first wire bonding area. The first die and the first wire bonding area are encapsulated with a molding material and a cavity with an opening is formed above the first die. The second wire bonding area is exposed in the cavity. A second die is placed in the cavity and electrically connected to the second wire bonding area such that the second die is electrically connected to the first die by way of the dummy lead.

Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.

Abstract: A packaged semiconductor device having an integrated circuit (IC) die, a flexible tube, and a metal slug. During assembly, a first end of the tube is mounted on a surface of the IC die and a second end of the tube extends away from the die surface. The exposed portions of the surface of the IC die are encased in a molding compound, which also encases the perimeter of the tube. After molding, the tube may be filled with metal to improve conduction of heat away from the die top. If the tube is formed of a soft material like rubber then the tube will not damage the die top during attachment thereto.