Abstract: A method of estimating a fragment count for the display of at least one three-dimensional (3D) object. The method comprises determining an ellipsoid representative of a set of vertices defined by coordinates of the at least one 3D object, applying a transformation to the ellipsoid, calculating a projection area of the transformed ellipsoid, and estimating the fragment count for the display of the 3D object based at least partly on the calculated projection area of the transformed ellipsoid.

Abstract: A capacitive keypad position sensor includes a keypad touch panel having a first defined key area disposed in a plane having first and second orthogonal axes. First and second electrodes respectively occupy first and second areas below the first defined key area. Each electrode includes a plurality of parallel rows extending along the first axis and spaced apart from one another along the second axis. Each of the plurality of rows has a length along the first axis that is substantially equal to a width of the first defined key area along the first axis measured at a position along the second axis corresponding to the respective one of the plurality of rows. At least some of the first and second pluralities of rows are interleaved with one another.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.

Abstract: The embodiments described herein can provide a variable reluctance sensor (VRS) interface that may reduce the probability of erroneous transitions in a resulting generated detect signal. As such, the VRS interface can improve the accuracy of position and/or motion determinations, and thus can improve the performance of a wide variety of devices that use variable reluctance sensors. To facilitate this, the VRS interface includes a pre-processing circuit configured to modify a VRS signal to prevent the modified VRS signal from dropping below a threshold value and generating erroneous transitions in the detect signal pulse between leading and lagging edges of a tooth. In one embodiment the pre-processing circuit comprises a peak and hold circuit. In another embodiment the pre-processing circuit comprises a resistor-capacitor circuit. In either case the pre-processing circuit can prevent erroneous transitions in the detect signal and thus may improve the performance and accuracy of the system.

Abstract: An approach is provided in which a design tool executes static timing analysis of an integrated circuit design using a first set of timing values corresponding to a first set of layout properties of a transistor included in a standard cell utilized by the integrated circuit design. When the design tool determines that the static timing analysis generates a timing violation within a violation budget, the design tool selects a second set of timing values of the standard cell corresponding to a second set of layout properties of the transistor. The design tool determines that re-execution of the static timing analysis using the second set of timing values resolves the timing violation and, in turn, generates mask layer data that includes the second set of layout properties.

Abstract: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.

Abstract: A clock generator suitable for use with memory devices enables generation of memory clock signals having odd or even division ratios, an optional phase shift and a 50% duty cycle. First and second clock gate circuits receive a base clock signal and an inverted version thereof, respectively, and are both gated by the output of two comparators that are set when a value of a down counter receiving the base clock signal reaches a predetermined value. The clock gate circuits each include a multiplexer and D-type flip-flop. The output from either flip-flop, or both their outputs ‘ORed’ together, may be used as a memory clock depending on the desired division ratio and phase shift. The generator is particularly suitable for DDR memory applications that require both edges of the clock signal are evenly placed for launching data on both rising and falling edges.

Abstract: A functional simulator with watchpoint support includes a CPU having a first-level DMI cache, a watchpoint manager having a second-level DMI cache, an interconnect module, and a memory controller. The simulator is operated by a front-end tool. Watchpoints corresponding to a predetermined memory addresses are set by the front-end tool and stored as a watchpoint address list in the watchpoint manager. When a memory access request is received by the first-level DMI cache, after a failure to complete the memory access request, the CPU transmits the request to the watchpoint manager. The watchpoint manager searches for a memory address associated with the memory access request in the watchpoint address list. If a match is found, the watchpoint manager generates a watchpoint hit signal and notifies the front-end tool.

Abstract: A method for assembling a quad flat no-lead (QFN) device includes mounting and electrically connecting a die to a pre-plated lead frame (PPF) to form a sub-assembly, where the plating is solder-wettable and the lead frame has notches in the lead fingers located along the device boundary. The sub-assembly is then encapsulated to (1) leave the distal ends of the lead fingers exposed and (2) have the edge of the encapsulant adjacent to the notches. The sub-assembly is then singulated to leave distal lead segments protruding from the resulting device. The protruding exposed segments are then bent to be substantially parallel to the device sidewalls. Consequently, the plated surface of each lead extends along portions of both the bottom and one side of the device.

Abstract: A method of measuring a capacitor value comprises the steps of loading the capacitor up to a given voltage value; obtaining a first measure of a time for discharging the capacitor by a fixed voltage drop, the discharge of the capacitor being caused by a first current; reloading the capacitor up to the given voltage value; obtaining a second measure of a time for discharging the capacitor by the fixed voltage drop, the discharge of the capacitor being caused by the first current and by a second current of known value added to said first current; and determining the capacitor value from the difference between the first measure and the second measure, based on the given voltage drop or the given time, respectively, and based further on the known value of the given second current.

Abstract: A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.

Abstract: A pressure sensor (20) includes a test cell (32) and sense cell (34). The sense cell (34) includes an electrode (42) formed on a substrate (30) and a sense diaphragm (68) spaced apart from the electrode (42) to produce a sense cavity (64). The test cell (32) includes an electrode (40) formed on the substrate (30) and a test diaphragm (70) spaced apart from the electrode (40) to produce a test cavity (66). Both of the cells (32, 34) are sensitive to pressure (36). However, a critical dimension (76) of the sense diaphragm (68) is less than a critical dimension (80) of the test diaphragm (70) so that the test cell (32) has greater sensitivity (142) to pressure (36) than the sense cell (34). Parameters (100) measured at the test cell (32) are utilized to estimate a sensitivity (138) of the sense cell (34).

Abstract: Methods and systems are disclosed for address mapping between die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Configurable address mapping is used to re-configure the host memory map to include expansion memory map details in a seamless fashion. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance.

Abstract: An integrated circuit device comprises at least one connectivity identification module. The at least one connectivity identification module is arranged to determine an initial sensed state of at least one external signal path of the integrated circuit device, cause the at least one external signal path to be pulled towards an opposing state to the initial sensed state therefor, determine a new sensed state of the at least one external signal path of the integrated circuit device, and identify a presence of a broken connection within the at least one external signal path, if the new sensed state of the at least one external signal path does not match the initial sensed state of the at least one external signal path.

Abstract: A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

Abstract: A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

Abstract: A decoding unit for decoding a signal modulating a plurality of symbols wherein each symbol carries a plurality of information which are code-division multiplexed in the time domain and in the frequency domain and wherein each information is associated with a known sequence of phase rotations, the phase in the known sequence varying deterministically between the plurality of symbols. The decoding unit first performs a phase rotation of the received plurality of symbols, then performs the time-domain despreading operation and finally performs the frequency-domain despreading operation. A processor, a receiver, a method and a computer program are also claimed.

Abstract: A fail-safe booting system suitable for a system-on-chip (SOC) automatically detects and rectifies failures in power-on reset (POR) configuration or boot loader fetch operations. If a failure due to a boot loader fetch occurs, a POR configuration and boot loader are fetched from a different non-volatile memory. The reloading takes place from further different non-volatile memory sources if the boot loader fetch fails again. The automated system operates in accordance with a state machine, and does not involve any manual, on-board switch selection or manual re-programming.

Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.

Abstract: A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region.