Abstract: A display control unit is connected to a display and arranged to generate a video signal representing a sequence of video frames to be displayed consecutively on said display. The display control unit may include a first memory unit arranged to buffer a set of image descriptors; a second memory unit connected between said first memory unit and said display; an update unit connected to said first memory unit and arranged to update said image descriptors in said first memory unit and to generate a proceed signal only when said set of image descriptors in said first memory unit is up to date; a copy unit arranged to copy said image descriptors from said first memory unit to said second memory unit in response to said proceed signal; and a video unit arranged to generate said video signal on the basis of said image descriptors in said second memory unit.

Abstract: A method and apparatus are provided for fabricating an electro-optical interconnect on an integrated circuit (101, 114) in which an optical circuit element (102) is formed by forming a cylinder-shaped conductive interconnect structure (120, 122, 126, 128) with one or more conductive layers formed around a central opening (129) which is located over an optically transparent layer (118) located over the optical circuit element (102).

Abstract: The embodiments described herein provide an antifuse that includes a substrate material and an isolation trench formed in the substrate material, where the isolation trench has a first side and a second side opposite the first side. An electrode is positioned above the substrate material and proximate to the first side of the isolation trench. An insulating layer is disposed between the electrode and the substrate material. So configured, a voltage or current applied between the electrode and the substrate material causes a rupture in the insulating layer and creates a current path through the insulating layer and under the isolation trench to the substrate material proximate the second side of the isolation trench.

Abstract: A sample-and-hold circuit is provided. The sample-and-hold circuit includes an input one or more dedicated capacitive elements, one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements, an output, a group of switches, and a control unit. The control unit controls said switches so as to interconnect said input, said one or more dedicated capacitive elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle.

Abstract: A receiver unit comprising a mixer, a test signal unit, a multiplexer unit, an amplifier unit, a signal strength unit, and a digital control unit is described. The mixer may be arranged to downconvert a received radio-frequency signal to an intermediate frequency, thereby generating a reception signal having the intermediate frequency. The multiplexer unit may be connected to the mixer and to the test signal unit and arranged to select, among the reception signal and a test signal, a multiplexer output signal in dependence on an operating signal. The amplifier unit may be connected to the multiplexer unit and arranged to amplify the multiplexer output signal, thereby generating an amplified signal. The signal strength unit may be connected to the amplifier unit and arranged to generate a signal strength indicator indicative of a signal strength of the amplified signal.

Abstract: A method of controlling operating parameters of a radio frequency power amplifier amplifying an input signal applied in bursts with controlled input power to an input of the power amplifier, comprising responding to gain variation parameters relating to variations in the scalar gain of said amplifier starting during an initial ramp-up period of a first burst to control supply voltage and quiescent current parameters for said amplifier during a subsequent burst.

Abstract: Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.

Abstract: A system for reducing in-phase and quadrature-phase (I/Q) impairments includes first, second, third, and fourth programmable registers for storing respective first, second, third, and fourth values, first and second finite impulse response (FIR) filters having respective first and second sets of filter taps, and first and second adders. The first FIR filter receives an I input signal and generates first and second intermediate output signals based on the first and second values for I and Q channels, respectively. The second FIR filter receives a Q input signal and generates third and fourth intermediate output signals based on the third and fourth values for the I and Q channels, respectively. The first and second adders receive the first and second, and the third and fourth intermediate output signals, respectively, and generate compensated I and Q output signals for the I and Q channels.

Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

Abstract: A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

Abstract: An advanced communication controller unit for a distributed communication system having a plurality of communication controller units, at least one being an advanced communication controller unit, each coupled to a communication medium and adapted to communicate using a communication is presented. The advanced communication controller unit comprises a protocol event recording circuit having a monitoring input connected to at least one protocol event data transmission path of the advanced communication controller unit and a debug output connected to a memory device; and adapted to filter protocol event data received from the monitoring input depending on at least one configuration parameter and to provide filtered protocol event data to the debug output. A method for recording protocol events using a protocol event recording circuit in an advanced communication controller unit and a vehicle comprising at least one advanced communication controller unit are also disclosed.

Abstract: A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.

Abstract: Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution mode(s). For example, in embodiments that employ cache storage organized as a set associative cache, partition may be achieved by reserving a subset of the ways in the cache for use when operating in lockstep mode. Some or all of the remaining ways are available for use when operating in non-lockstep execution mode(s). In some embodiments, a subset of the cache sets, rather than cache ways, may be reserved in a like manner, though for concreteness, much of the description that follows emphasizes way-partitioned embodiments.

Abstract: A method of managing a memory of an apparatus includes maintaining a plurality of lists of identifiers that each has an associated size value, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes. When a process requests allocation of a region of the memory: one of the lists is identified that has an associated size value suitable for the allocation request; and if that list is not empty, a region of the memory is identified to the process by one of the identifiers that identifier is removed from that list, and, otherwise, a region of the memory is allocated with a size of the identified associated size value and the allocated region of the memory is identified the process.

Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.

Abstract: A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (?0, ?1, . . . ?v?1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2??0, ej2??1, . . . ej2??v?1) that may be rearranged by a permutation unit (286) for use by vector data path.

Abstract: A voltage clamping circuit that is implemented using low voltage devices provides a way to discharge an input/output pin to ground during overvoltage conditions and to avoid any interaction between the input/output pin and the input/output supply during clamping action. The voltage clamping circuit is also self-protected. A voltage detection circuit detects an overvoltage condition and in response generates a signal that turns on a PMOS, which in turn provides a clamping current path between the input/output pin and ground.

Abstract: A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.

Abstract: A method and apparatus are provided for error correction of a memory by using a first memory (18) and second memory (14) to perform error correction code (ECC) processing on data retrieved from the first memory and to use status control bits (35-37) in the second memory to detect and manage hard and soft errors identified by the ECC processing.

Abstract: A method and apparatus for selecting data path elements for cloning within an integrated circuit (IC) design is described. The method comprises performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.