Abstract: An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node.

Abstract: A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.

Abstract: The present invention pertains to a linear power regulator device that includes an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output. The linear power regulator device also includes an external connection connectable or connected to an external pass device; and the driver device is arranged to drive the external pass device via the driver output and the external connection.

Abstract: A statistical power indication monitor including a random pattern generator that generates random sample assertions of a sample signal, a total counter that counts a total number of the random sample assertions within a sample time interval, detect logic that provides a detection signal for each power indication signal that is asserted coincident with the sample signal, and counter logic that counts a number of assertions of each detection signal during the sample time interval. The assertion count of each power indication signal divided by the total count provides a statistical indication of power consumption of a corresponding system. A user may use the statistical monitoring information to adjust system or application operation. The random pattern generator may be a pseudo-random pattern generator including a linear feedback shift register and may have programmable seed and sample rate.

Abstract: A method and apparatus for performing touch detection within a touch sensing application is described. Touch sensor signal data is received, a first filtering of the received touch sensor signal data to create a first filtered data signal is performed, a second filtering of the received touch sensor signal data to create a second filtered data signal is also performed, a difference between the first and second filtered data signals to determine a delta value is calculated, and an occurrence of a touch based at least partly on the determined delta value is determined.

Abstract: Systems and methods for managing cold-crank events. In an embodiment, a method may include detecting a cold-crank event and setting a switching circuit to a non-conductive state, where the switching circuit is configured to couple a first regulator to a memory circuit such that setting the switching circuit to the non-conductive state de-couples the memory circuit from the first regulator. The method may also include setting the switching circuit to a conductive state in current limitation mode during a recovery period following the cold-crank event to re-couple the memory circuit to the first regulator. In another embodiment, an electronic device include a switching circuit, a first regulator coupled to a first terminal of the switching circuit, a second regulator coupled to a second terminal of the switching circuit, a logic circuit coupled to the switching circuit, and a memory circuit coupled to the second terminal of the switching circuit.

Abstract: An integrated circuit (IC) device, and method therefor, the IC device comprising a plurality of self-test components arranged to execute self-tests in parallel during a self-test execution phase of the IC device, and at least one clock control component arranged to provide at least one clock signal to the plurality of self-test components at least during the self-test execution phase of the IC device. The at least one clock control component is further arranged to receive at least one indication that self-testing has ceased within at least a first self-test component, and dynamically modulate the at least one clock signal provided to at least one further self-test component for which self-testing has not ceased to increase a clock rate of the at least one clock signal upon receipt of an indication that self-test execution has ceased within the at least first self-test component.

Abstract: A conference call system comprises an input interface for receiving during a conference call at least two input streams of audio signal, each from another source. A selection unit is connected to the input interface, for selecting a number of dominant speaker streams out of the input streams, the number being less than or equal to a maximum number of dominant speakers value and each of the dominant speaker streams representing speech from a respective dominant speaker. A mixer is connected to the selection unit, for mixing the selected streams into an output stream. The conference call system comprises an output interface for outputting the output stream and a selection control unit connected to the selection unit and the input interface, for dynamically setting, during the conference call, the maximum number of dominant speakers value based on dynamics of the conference call.

Abstract: A structure and method to improve saw singulation quality and wettability of integrated circuit packages (140) assembled with lead frames (112) having half-etched recesses (134) in leads. A method of manufacturing lead frames includes providing a lead frame strip (110) having a plurality of lead frames. Each of the lead frames includes a depression (130) that is at least partially filled with a material (400) prior to singulating the lead frame strip.

Abstract: Methods and systems for producing random numbers include a random number generator with a first port and a second port. The first port is configured to receive a first type of random data request, and the random number generator is configured to generate first random data while the first type of request is asserted on the first port. The second port is configured to receive a second type of random data request, and the random number generator is configured to generate only a specified length of second random data in response to receiving the second type of request on the second port. An embodiment of a system also includes a data structure configured to store multiple random values, which are derived from the first random data generated by the random number generator in response to the first type of random data request.

Abstract: A data processing system having a first processor, a second processor, a local memory of the second processor, and a built-in self-test (BIST) controller of the second processor which can be randomly enabled to perform memory accesses on the local memory of the second processor and which includes a random value generator is provided. The system can perform a method including executing a secure code sequence by the first processor and performing, by the BIST controller of the second processor, BIST memory accesses to the local memory of the second processor in response to the random value generator. Performing the BIST memory accesses is performed concurrently with executing the secure code sequence.

Abstract: An integrated circuit device comprises at least one digital to analogue converter module. The DAC module includes at least one current replicator component having a first channel terminal, a second channel terminal and a reference voltage terminal arranged to receive a reference voltage signal; the at least one current replicator component being arranged to moderate a current flowing between the first and second channel terminals based at least partly on the received reference voltage signal. The DAC module also includes at least one filter component coupled to the reference voltage terminal to perform filtering of the reference voltage signal.

Abstract: A mold compound is provided for encapsulating a semiconductor device (101). The mold compound comprises at least approximately 70% by weight silica fillers, at least approximately 10% by weight epoxy resin system, and beneficial ions that are beneficial with respect to copper ball bond corrosion. A total level of the beneficial ions in the mold compound is at least approximately 100 ppm.

Abstract: An integrated package is disclosed that includes a conductive structure that can be selectively configured to include a radiating element of a planar antenna or to include a radio-frequency shielding structure. Examples of a planar antenna include PIFA antennas, patch antennas, and the like. The planar antenna can be selectively configured to different tuning profiles, and operate as a diversity antenna by alternating its tuning profile configuration amongst different tuning profiles.

Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

Abstract: Power switches with current limitation and zero Direct Current (DC) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero DC power outside of the transition period. In another embodiment, a method includes controlling, via a switching circuit coupled between a voltage supply and an integrated circuit, an amount of current drawn by the integrated circuit from the voltage supply during a transition period; and causing the switching circuit to consume no static power during periods of time other than the transition period.

Abstract: An integrated circuit and a method. The integrated circuit includes an internal component having an output for providing a driven input signal; an output driver, connected to the internal component, for converting said driven input signal in an output signal; an output pad for outputting said output signal to a component outside the integrated circuit; a power grid configured to supply a supply voltage to the output driver; a controllable current consuming component connected to the power grid, said connectable current consuming component being controllable to consume current in accordance with a supply voltage change reduction pattern; a change detector connected to the internal component and the controllable current consuming component, for detecting a change in said driven input signal prior to said change resulting in a change in said output signal and to control said current consuming component to consume current in response to said detecting.

Abstract: Embodiments of methods of fabricating a sensor device includes attaching a first wafer to a sensor wafer with a first bond material, and attaching a second wafer to the sensor wafer with a second bond material, the second bond material having a lower bonding temperature than the first bond material. After attaching the second wafer, an opening (e.g., a trench cut) through the second wafer is formed, and an adhesive material is provided through the opening to further secure the second wafer to the sensor wafer. Embodiments of sensor devices formed using such methods include a first device cavity having a first pressure, and a second device cavity having a second pressure.

Abstract: A signal detector is configured to detect a signal of interest in a received signal. The received signal may comprise noise. The signal of interest is oscillatory at least during one or more time segments. The signal detector comprises a frequency discriminator arranged to determine an instantaneous frequency of the received signal, an evaluator arranged to determine an amount of change of the instantaneous frequency during a test interval, and a comparator arranged to determine whether the amount of change is below a given threshold. The signal of interest may be digitally modulated. In this case the test interval may be shorter than the duration of one data bit in the signal of interest. In a related aspect, a signal transmission system comprises a signal generator for generating a signal of interest and a signal detector for detecting the signal of interest in a received signal. A method of detecting a signal of interest in a received signal is also proposed.

Abstract: A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.