Abstract: A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.

Abstract: A resistive random access memory (ReRAM) device can comprise a first metal layer and a first metal-oxide layer on the first metal layer. The first metal-oxide layer comprises the first metal. A second metal layer can comprise a second metal over and in physical contact with the first metal-oxide layer. A first continuous non-conductive barrier layer can be in physical contact with sidewalls of the first metal layer and sidewalls of the first metal-oxide layer. A second metal-oxide layer can be on the second metal layer. The second metal-oxide layer can comprise the second metal layer. A third metal layer can be over and in physical contact with the second metal-oxide layer. The first and second metal-oxide layers, are further characterized as independent storage mediums.

Abstract: Embodiments include bitstring generators and methods of their operation. A sampling parameter of the bitstring generator is set to a current value, and values of one or more bits are then repeatedly sampled based on the current value of the sampling parameter. The repeated sampling results in a set of test bits, which is analyzed to determine a randomness measurement associated with the set of test bits. A determination is made whether the randomness measurement meets a criterion. If not, the current value of the sampling parameter is changed to a different value that corresponds to a lower probability of being able to correctly predict the values of the one or more bits produced by the bitstring generator. The steps of repeatedly sampling, analyzing the set of test bits, and determining whether the randomness measurement meets the criteria are then repeated.

Abstract: A die temperature measurement system (300) includes an external test environment setup (352) and an integrated circuit (302). The external test environment setup (352) includes means to force and accurately measure electrical variables. The integrated circuit (302) includes a bipolar transistor (325); a selectable switch (340) for selecting from plurality of integrated resistances (342, 344) to be coupled in series between a base (322) of the bipolar transistor and a first input (362); and a selectable-gain current mirror (310) with a gain, a programmable current-mirror output coupled to the collector (326) of the bipolar transistor. The bipolar transistor and optional diodes (335) are sequentially biased with a set of proportional collector current levels. For each bias condition, the temperature-dependent voltage produced by the structure is extracted and stored. Die temperature is obtained through algebraic manipulation (450) of this data. Parasitic resistance and I/O pad leakage effects are canceled.

Abstract: Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.

Abstract: A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value.

Abstract: An integrated circuit device comprising at least one voltage supply module arranged to receive at an input thereof at least one control signal and to provide at an output thereof a voltage signal in accordance with the received at least one control signal, and at least one control module comprising at least one feedback loop between the output of the at least one voltage supply module and the input of the at least one voltage supply module, and arranged to generate the at least one control signal based at least partly on the voltage level of the voltage signal output by the at least one voltage supply module. The at least one control module is further arranged to receive at an input thereof at least one instantaneous indication of a load current at the output of the at least one voltage supply module, and apply a compensation to the at least one control signal provided to the at least one voltage supply module based at least partly on the received at least one indication of the load current.

Abstract: A drive-mode oscillator module for use within a micro-electro-mechanical system (MEMS) device is described. The drive-mode oscillator module is arranged to receive a proof-mass measurement signal from a proof-mass of the MEMS device and to output a proof-mass actuation signal to the proof-mass of the MEMS device. The drive-mode oscillator module comprises a first, higher gain accuracy drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during an active mode of the MEMS device, and a second, lower power consumption drive-mode component for generating an actuation signal to be output by the drive-mode oscillator module during a standby mode of the MEMS device.

Abstract: A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable (e.g., high voltage operations) can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching can be provided for just a small area of the possible flash memory map, and program flow can be controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

Abstract: An integrated circuit package includes a die having a first substrate implementing an integrated circuit comprising circuit elements. The die includes a first plurality of metal layers implementing a first portion of a metal interconnect structure for the integrated circuit. The die also includes a first plurality of pads at or overlying a top metal layer of the first plurality of metal layers. The integrated circuit package includes an interposer having a second plurality of metal layers implementing a second portion of the metal interconnect structure. The interposer includes a second plurality of pads at or overlying a top metal layer of the second plurality of metal layers. A plurality of solder structures couple the first and second pluralities of pads. The first and second portions of the metal interconnect structure together complete a signal path between two or more circuit blocks of the integrated circuit.

Abstract: In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. When the first portion of the address has a second value, a second one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry.

Abstract: A power switching device connected or connectable between a power supply and a load is described. The device may have at least two different operating states, each operating state having a different level of said output voltage associated with it.

Abstract: A charging circuit for a bootstrap capacitor comprises a P MOSFET having a body diode and an N channel power MOSFET also having a body diode. The drain of the P MOSFET is coupled to the source of the N channel power MOSFET, and the source of the P MOSFET receives current from a vehicle's battery. The gate of the P MOSFET receives a control signal for turning the P MOSFET either on or off and the drain of the N channel power MOSFET is connected to a bootstrap capacitor The P MOSFET's body diode prevents current flow from the battery to the bootstrap capacitor when the P MOSFET is turned off and the N MOSFET's body diode prevents current flow from the bootstrap capacitor to the battery when the N MOSFET is turned off. The use of a power MOSFET device with its low ON resistance ensures that the capacitor is charged to a sufficiently high voltage even under low battery conditions.

Abstract: A method of sensing a user input to a capacitive touch sensor having a sense electrode is described. The method comprises obtaining a measure of capacitance of the sense electrode of the capacitive touch sensor, determining an indication of contact between a finger of a user and the capacitive touch sensor from comparing the measure of capacitance to a first threshold and determining an indication of exceeding a minimum pressure exercised by the finger of the user on the capacitive touch sensor from comparing the measure of capacitance to a second threshold, the second threshold being different from the first threshold. A capacitive touch sensor controller being arranged to perform such method is described. An input device for receiving user input is described. The input device comprises a capacitive touch sensor and such capacitive touch sensor controller.

Abstract: An approach is provided in which an equivalence class generator selects a configurable module that includes control points and configuration parameters. The configuration parameters define a parameter state space of the configurable module. The equivalence class generator utilizes the control points to generate equivalence classes, which include class representatives that indicate values for the configuration parameters. Next, one of the class representatives are selected and verified from each of the equivalence classes. In turn, the verification of the class representatives verifies the parameter state space of the configurable module.

Abstract: An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.

Abstract: Methods of manufacturing a flat-pack no-lead microelectronic package (2100) coat exposed base metal at a cut end of a lead frame of the package with solder (1001). One method coats the exposed base metal with solder when the package is in a strip (200, 300). Another method coats the exposed base metal with solder after the package is singulated. As a result, all portions of leads of the package that may receive solder during mounting of the package to a printed circuit board are solder wettable. A solder wettable lead end (504) on the package facilitates formation of a solder fillet during mounting of the package.

Abstract: A circuit having an active mode and a sleep mode includes a power transistor, an amplifier, and a protection circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit for coupling to a load, and a control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the control electrode and the first current electrode during the sleep mode. The amplifier has an output coupled to the control electrode of the power transistor that provides an active output during the active mode. The protection circuit detects the leakage current and prevents the leakage current from developing a voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.