Abstract: A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.

Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.

Abstract: In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.

Abstract: A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.

Abstract: A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

Abstract: A system (and a method) are disclosed for a video processing system with enhanced entropy coding performance. The system includes an entropy decoder configured to divide decoding of an input video stream into arithmetic decoding and syntax decoding. The entropy decoder includes an arithmetic decoding module, a syntax decoding module, a memory management module and a memory buffer connecting the two decoding modules. The arithmetic decoding module is configured to decode the input video stream into multiple bins of decoded input video stream and the syntax decoding module is configured to decode the bins of arithmetically decoded input videos stream into one or more syntax elements. The memory management module uses the memory buffer to accelerate the coding performances of arithmetic decoding and syntax decoding. The system also includes a corresponding entropy encoder configured to encode a video stream with improved coding performance.

Abstract: A method of making a semiconductor device having a substrate includes forming a first interconnect layer over the substrate, wherein a first metal portion of a first metal type is within the first interconnect layer and has a first via interface location. An interlayer dielectric is formed over the first interconnect layer. An opening in the interlayer dielectric is formed over the via interface location of the first metal portion. A second interconnect layer is formed over the interlayer dielectric. A second metal portion and a via of the first metal type is within the second interconnect layer. The via is formed in the opening to form an electrical contact between the first metal portion and the second metal portion. The via is over the first via interface location. A first implant of the first metal type is aligned to the first via interface location.

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates (118, 128) on a first substrate area (111) which are encapsulated in one or more planar dielectric layers (130) prior to forming in-laid high-k metal select gates and CMOS transistor gates (136, 138) in first and second substrate areas (111, 113) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: A stacked semiconductor device includes a first and second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first and second semiconductor devices include active circuitry. The first and second semiconductor devices are stacked so that the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device. At least one continuous conductive via extends from the second major surface of the first semiconductor device to the first major surface of the second semiconductor device. Conductive material fills a cavity adjacent to the contact pad and is in contact with one side of the contact pad. Another side of the contact pad of the first semiconductor device faces and is in contact with another side of the contact pad of the second semiconductor device.

Abstract: A method of performing a write operation on memory cells of a memory array includes applying a first plurality of pulses the write operation on the memory cells in accordance with a first predetermined ramp rate, wherein the first plurality of pulses is a predetermined number of pulses; performing a comparison of a threshold voltage of a subset of the memory cells with an interim verify voltage; and if a threshold voltage of any of the subset of memory cells fails the comparison with the interim verify voltage, continuing the write operation by applying a second plurality of pulses on the memory cells in accordance with a second predetermined ramp rate which has an increased ramp rate as compared to the first predetermined ramp rate.

Abstract: A scan flip-flop includes a multiplexer, a flip-flop, and a logic circuit. The flip-flop includes a transmission gate that has two sets of clock-controlled transistors. The combined width of the clock-controlled transistors in a set equals the width of the single transistor commonly used in known scan flip-flop circuits. The logic circuit inhibits the clock signal from reaching one transistor of each set during scan mode, which reduces power consumption without sacrificing speed of operation.

Abstract: A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).

Abstract: Methods and systems are disclosed for recovering dirty linefill buffer data upon linefill request failures. When a linefill request failure occurs and the linefill buffer has been marked as dirty, such as due to a system bus failure, the contents of the linefill buffer are pushed back to the system bus. The dirty data within the linefill buffer can then be used to update the external memory. The disclosed embodiments are useful for a wide variety of applications, including those requiring low data failure rates.

Abstract: A MEMS device (20) includes a proof mass structure (26) and beams (28, 30) residing in a central opening (32) of the proof mass structure (26), where the structure and the beams are suspended over a substrate (22). The beams (28, 30) are oriented such that lengthwise edges (34, 36) of the beams are beside one another. Isolation segments (38) are interposed between the beams (28, 30) such that a middle portion (40) of each of the beams is laterally anchored to adjacent isolation segments (38). The isolation segments (38) provide electrical isolation between the beams. The beams (28, 30) are anchored to the substrate (22) via compliant structures (61, 65) that isolate the beams from deformations in the underlying substrate. The compliant structures (61, 65) provide electrically conductive paths (96, 98) to the substrate (22) for the beams (28, 30) where the paths are electrically isolated from one another.

Abstract: In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.

Abstract: A channel estimation processor for a receiver in a wireless communication system is described. The channel estimation processor includes a stage-1 processor (STG1) arranged to pluralities of Nsym reference symbol correlation values per slot. The channel estimation processor includes a stage-2 processor (STG2) comprising a plurality of stage-2a processors for obtaining filtered outputs per slot, a respective plurality of stage-2b processors for obtaining respective slot filter results and a stage-2 adder (STG2ADD) for obtaining channel estimates for respective anchor positions. The stage-2a processors are arranged to filter respective pluralities of reference symbol correlation values using respective reference symbol filters (ga) to obtain a respective filtered output per slot.

Abstract: A digital signal processor (300), compatible with the Common Public Radio Interface (CPRI), permits reading and writing of IQ data of antenna carriers which have two different sampling rates by using just two single sample rate DMA (Direct Memory Access) modules (306,313). The digital signal processor (300) is capable of processing data of different sampling rates on just one CPRI lane comprising one framer (302). This is achieved by incorporating a divider module (307) and a multiplexer module (314) between the framer (302) and system memory (309, 315). The processor (300) may also be configured so that single sampling rates can also be accommodated.

Abstract: A reference voltage loss monitoring circuit having a first and second reference node. The reference nodes are connected to a voltage reference. A first connection device is connects the first reference node to the second reference node, and includes a first diode to allow a current flowing from the first reference node to the reference ground node and not conversely. The first diode includes a first main transistor. A second connection device connects the second reference node to the first reference node, and includes a second diode to allow a current flowing from the second reference node to first reference node and not conversely. The second diode includes a second main transistor. Each of the first and second connection devices further includes a secondary transistor mirrored with the main transistor of the connection devices.

Abstract: A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.

Abstract: An embodiment of an electrical device includes a device package and a plurality of amplifier paths physically contained by the device package. Each amplifier path includes an amplifier stage electrically coupled between an input and an output to the amplifier stage, and the amplifier stages of the plurality of amplifier paths are symmetrical. In a further embodiment, the amplifier paths have translational symmetry within the device package. In another further embodiment, transistors comprising the amplifier stages of the plurality of amplifier paths are substantially identical in size. The electrical device may be incorporated into an amplifier system that further includes an external input network and an external output network. For example, the amplifier system may be configured in a Doherty amplifier topology.