Abstract: During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.

Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.

Abstract: A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor.

Abstract: A microelectronic assembly (100) and a microelectronic device (4100) include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.

Abstract: A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.

Abstract: A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.

Abstract: An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.

Abstract: The present invention pertains to a linear power regulator device, comprising an internal pass device, a driver device having a driver output arranged to drive the internal pass device via the driver output, wherein the linear power regulator device comprises an external connection connectable or connected to an external pass device; and wherein the driver device is arranged to drive an external pass device via the driver output and the external connection. The invention also pertains to a corresponding electronic device.

Abstract: A method of scrolling a data set stored in a memory across a screen is described. The method comprises presenting a user interface widget on the screen. The user interface widget comprises one or more linear scroll bars and a rotation-sensitive scroll area. The method further comprises receiving one or more user inputs to the user interface widget, determining at least a scroll speed, a scroll direction and a scroll resolution from the one or more user inputs to obtain a scroll control signal, and scrolling the data set across the screen in accordance with the scroll control signal. A computer program product comprising instructions for causing a processor system to perform a method of scrolling a data set stored in a memory across a screen is described. A user interface widget is described. A device comprising a processor arranged to perform such method is described.

Abstract: A system-on-chip comprises a plurality of functional domains. The plurality of functional domains comprise a first domain and a second domain, the first domain having a first active mode of operation and the second domain having a second active mode of operation different from the first active mode of operation. The system-on-chip also comprises a control unit operably coupled to the first and second domains and capable of placing the first domain in the first active mode and the second domain in the second active mode so that the first domain is in the first active mode and the second domain is in the second active mode substantially contemporaneously. The first active mode of operation is functionally different from the second active mode of operation.

Abstract: A digital sample clock generator for generating a sample clock signal from an input signal derived from a drive measurement voltage signal of a vibrating MEMS gyroscope is provided.

Abstract: A CMOS cell incorporated on an integrated circuit including a PMOS transistor and an NMOS transistor. The current terminals of the PMOS and NMOS transistors are coupled in series between a lower voltage supply rail and a reference rail. The well connection of the PMOS transistor is coupled to an upper voltage supply rail having a voltage level greater than the lower voltage supply rail. The CMOS cell has low voltage swing and low leakage current to reduce power consumption. A second PMOS and NMOS transistor pair may be included and coupled in similar manner and to the first PMOS and NMOS pair to form a non-inverting cell. The PMOS transistors may be implemented in an N-well that is conductively tied to the upper supply voltage rail to avoid isolation barriers. The cell may be used in a clock tree to significantly reduce power consumption of the integrated circuit.

Abstract: A BGA type packaged integrated circuit (IC) die has an exposed coronal heat spreader. The die, which is attached to a substrate, is encapsulated in a central segment of molding compound. The central segment is laterally surrounded by, and separated by a moat from a ring segment of molding compound, to a form a slot. The coronal heat spreader is inserted into the slot to cap the central segment. The coronal heat spreader is attached to the substrate and to the central segment with thermal glue. In operation, at least some of the heat generated by the die is dissipated through the coronal heat spreader.

Abstract: A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.

Abstract: A method for enabling access to functionality provided by resources outside of an operating system environment is provided. The method includes: receiving a call for functionality provided by resources outside of the operating system environment; and copying function parameters from within the received call to an area of memory accessible to the resources outside of the operating system environment that provide the called functionality.

Abstract: An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.

Abstract: A display controller includes a controller input connectable to receive first image data representing a non-safety relevant part of an image to be displayed on a display and to receive second image data representing a safety relevant part of the image. A merging unit is connected to the controller input, for composing the image from the first image data and second image data. A controller output is connectable to the display, for outputting display data representing the image. An image monitor is connected to the controller output, for comparing a part of the image corresponding to the safety relevant part with an reference for the part.

Abstract: A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analog sine and cosine waveforms indicative of fine position data and binary counterparts of the analog sine and cosine waveforms (Phase_A and Phase_B) indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analog sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analog sine and cosine signals and the digital representation thereof of the Sin-Cos sensor.

Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44?, 45?) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1?, 52-1?, 94, 94?, 94?) overlying the substrate (60). The active transistor(s) (41?) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42?, 43?) are also formed over the front face (63) of the substrate (60). Various terminals (42-1?, 42-2?, 43-1, 43-2?,50?, 51?, 52?, 42-1?, 42-2?, etc.) of the transistor(s) (41?), capacitor(s) (42?, 43?) and inductor(s) (44?, 45?) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98?) to minimize parasitic resistance.

Abstract: A method for assembling a 3D integrated circuit package that includes a base device and a top device. The method includes bonding (i) a pre-formed via array having a via rack and via elements and (ii) a base die to the substrate of the base device. The resulting sub-assembly is encapsulated in molding compound, and the via rack and any corresponding molding compound are removed, such as by grinding, to generate a base device with vias corresponding to the via elements and exposed bond posts on its top surface corresponding to the tops of the vias. A pre-packaged or unpackaged top device is then attached and bonded to the base device and, if necessary, encapsulated to form the 3D package with the exposed tops of the vias providing electrical connections between the base substrate and the top device.