Patents Assigned to Freescale
  • Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof
    Patent number: 9064977
    Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: June 23, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Zhiwei Gong (Tony), Michael B Vincent, Scott M Hayes, Jason R Wright
  • Integrated circuit device and method for generating a tuning signal for calibrating a voltage controlled oscillator
    Patent number: 9065450
    Abstract: An integrated circuit device comprises tuning signal circuitry for generating a tuning signal for calibrating a voltage controlled oscillator (VCO). The tuning signal circuitry is arranged to receive a target voltage signal that is representative of a target voltage across at least one passive element within a resonant tank circuit of a VCO that is being calibrated, generate a VCO simulation signal representative of an average voltage difference across at least one active component of the VCO that is being calibrated, and output a tuning signal based at least partly on the received target voltage signal and the generated VCO simulation signal.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: June 23, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lionel Geynet, Jean-Stephane Vigier
  • Voltage scale-down circuit
    Patent number: 9065441
    Abstract: A circuit for scaling down first and second input voltages includes first and second voltage scale-down circuits that scale down the first and second input voltages, respectively. The first voltage scale-down circuit includes a transistor that receives the first input voltage at its gate and, operating in a source-follower configuration, scales down the first input voltage to generate a first output voltage at its source. The second voltage scale-down circuit is identical to the first voltage scale-down circuit and generates a second output voltage based on the second input voltage.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: June 23, 2015
    Assignee: FREESCALE SEMICONDUCOTR, INC.
    Inventors: Nidhi Chaudhry, Ravi Dixit, Parul K. Sharma
  • Cavity based packaging for MEMS devices
    Patent number: 9061885
    Abstract: A wafer structure (88) includes a device wafer (20) and a cap wafer (60). Semiconductor dies (22) on the device wafer (20) each include a microelectronic device (26) and terminal elements (28, 30). Barriers (36, 52) are positioned in inactive regions (32, 50) of the device wafer (20). The cap wafer (60) is coupled to the device wafer (20) and covers the semiconductor dies (22). Portions (72) of the cap wafer (60) are removed to expose the terminal elements (28, 30). The barriers (36, 52) may be taller than the elements (28, 30) and function to prevent the portions (72) from contacting the terminal elements (28, 30) when the portions (72) are removed. The wafer structure (88) is singulated to form multiple semiconductor devices (89), each device (89) including the microelectronic device (26) covered by a section of the cap wafer (60) and terminal elements (28, 30) exposed from the cap wafer (60).
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 23, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC
    Inventors: Lisa H. Karlin, Lianjun Liu, Alex P. Pamatat, Paul M. Winebarger
  • Microprocessor systems and methods for a combined register file and checkpoint repair register
    Patent number: 9063747
    Abstract: In a processor, a decode unit identifies instructions needing a checkpoint and enables selected checkpoints. A register file unit includes a plurality of architectural registers. A first set of checkpoint registers correspond to a first checkpoint. Each checkpoint register corresponds to a corresponding architectural register. A first set of indicators correspond to the first set of checkpoint registers to indicate whether the corresponding architectural register has been modified or is intended to be modified prior to enabling of the first checkpoint. A second set of indicators correspond to the first set of checkpoint registers and indicate whether the corresponding architectural register has been modified or is intended to be modified after enabling the first checkpoint.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: June 23, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thang M. Tran
  • SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING
    Publication number: 20150170986
    Abstract: A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Margaret A. Szymanowski, Sarmad K. Musa, Fernando A. Santos, Mahesh K. Shah
  • DATA PATH CONFIGURATION COMPONENT, SIGNAL PROCESSING DEVICE AND METHOD THEREFOR
    Publication number: 20150169494
    Abstract: A data path configuration component for configuring at least one data path setting within a signal processing device is described. The data path configuration component is arranged to receive an indication of an operating mode of the signal processing device, and dynamically configure the at least one data path setting within the signal processing device based at least partially on the received indication of an operating mode of the signal processing device.
    Type: Application
    Filed: July 3, 2012
    Publication date: June 18, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Alistair Robertson, Manfred Thanner
  • LEVEL SHIFTER CIRCUIT
    Publication number: 20150171866
    Abstract: A level shifting circuit that includes a level shifter and a circuit stage. The circuit stage includes a pair of diodes circuits. The circuit stage includes a first output node and a second output node. The first output node is coupled via a current path to a first output of the level shifter and the second output node is coupled to via a current path to a second output of the level shifter. One of the diodes is coupled to the first output node and a power supply terminal. The other diode is coupled to the second output node and the power supply terminal.
    Type: Application
    Filed: December 18, 2013
    Publication date: June 18, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Kerry A. Ilgenstein, Gilles J. Muller
  • ETHERCAT PACKET FORWARDING WITH DISTRIBUTED CLOCKING
    Publication number: 20150172220
    Abstract: An EtherCAT packet forwarding system with distributed clocking is provided. The system comprises a master device and a plurality of slaves. The master comprises a processing port and a forward port for being respectively coupled to the at least two Ethernet ports of the master device in a redundant ring topology. The slaves comprise an internal clock indicating a current time, and a slave memory comprising a processing timestamp variable, a forwarding timestamp variable, a temporary timestamp variable and a copy-direct bit.
    Type: Application
    Filed: July 2, 2012
    Publication date: June 18, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Hezi Rahamim, Amir Yosha
  • METHOD AND APPARATUS FOR MULTI-CHIP STRUCTURE SEMICONDUCTOR PACKAGE
    Publication number: 20150171057
    Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A method may include providing the die carrier, melting the die attach material at a temperature in excess of 240° C. to attach the die to the surface of the die carrier to form a sub-assembly, attaching the sub-assembly to a leadframe, electrically interconnecting the die and the leadframe, and enclosing at least portions of the die and the leadframe to form a packaged device.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: FERNANDO A. SANTOS, AUDEL A. SANCHEZ, LAKSHMINARAYAN VISWANATHAN
  • Flip-flop having shared feedback and method of operation
    Patent number: 9059687
    Abstract: A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After coupling the first node to the second node, an inversion is enabled from the second node to a third node. An inversion from the third node to the fourth node is provided. After the enabling the inversion from the second node to the third node, the first node is decoupled from the second node. After the enabling the inversion from the second node to the third node, the second node is coupled to the third node. An inversion from the fourth node to the third node is enabled and the second node is decoupled from the fourth node.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: June 16, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Ravindraraj Ramaraju, Prashant U. Kenkare
  • Method for forming die assembly with heat spreader
    Patent number: 9059144
    Abstract: A method for forming a molded die assembly includes attaching a first major surface of a semiconductor die onto a package substrate; attaching a heat spreader to a second major surface of the semiconductor die, wherein the second major surface is opposite the first major surface, and wherein the semiconductor die, package substrate, and heat spreader form a die assembly; conforming a die release film to a transfer mold; closing the transfer mold around the die assembly such that the die release film is compressed against the heat spreader and a cavity is formed around the die assembly; transferring a thermoset material into the cavity; and releasing the die assembly from the die release film and the transfer mold.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: June 16, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo M. Higgins, III, Burton J. Carpenter, Glenn G. Daves
  • Resurf high voltage diode
    Patent number: 9059008
    Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: June 16, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Hongning Yang, Jiang-Kai Zuo
  • System, apparatus and method for translating data
    Patent number: 9058203
    Abstract: A distributed processor-based system comprises a plurality of communicating platforms, wherein a number of platforms in the distributed processor-based system comprise at least one compiler, the at least one compiler being operably coupled to data type translation logic and arranged to generate a memory layout for the respective platform. In response to an indication for a communication to occur between a first platform and a second platform the data type translation logic translates a memory layout using data type attributes for data to be transferred from the first platform to the second platform based on at least one platform-specific characteristic, such that the data does not require translating when received at the second platform.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: June 16, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Madalin Broscaru, Christian Caciuloiu
  • Trace correlation for profiling subroutines
    Patent number: 9058421
    Abstract: In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a trace unit coupled to the at least one core. A call to a subroutine can be detected, and in response, a program trace correlation (PTC) message can be generated and sent to a trace port. Data associated with an execution of the subroutine and/or performance of the data processing system can be sampled and sent to the trace port. A return from the subroutine can be detected, and in response, a trace message can be generated and sent to the trace port. The PTC message and the trace message can be correlated, and the correlation of the PTC message and the trace message can be used to determine a boundary for the subroutine and/or the sampled data associated with the execution of the subroutine.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: June 16, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zheng Xu, Richard G. Collins, Jason T. Nearing
  • System, method and program product for determining execution flow of the scheduler in response to setting a scheduler control variable by the debugger or by a processing entity
    Patent number: 9058206
    Abstract: A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: June 16, 2015
    Assignee: Freescale emiconductor, Inc.
    Inventors: Hillel Avni, Serge Lamikhov, Dov Levenglick
  • CLOCK FOR SERIAL COMMUNICATION DEVICE
    Publication number: 20150163046
    Abstract: Versatility and flexibility of integrated circuits can be accomplished by remote control via a serial interface, such as SPI. Read/write accesses to the SPI slave node can be achieved according to SPI protocol by the master node. Additionally, a state machine associated to the slave node SPI needs a local clock to exercise the control of the analog functions following a write access. The serial protocol defines a serial data word transfer to comprise a number of reserved clock cycles that are not assigned for communicating a data bit value of the data word. The slave device comprises a clock unit coupled to the serial clock line for providing a derived clock based on reserved clock cycles. The derived clock is used internally in the slave device to perform internal synchronous operations.
    Type: Application
    Filed: May 29, 2012
    Publication date: June 11, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Olivier Doare, Christophe Landez
  • VOLTAGE RECULATOR CIRCUIT AND METHOD THEREFOR
    Publication number: 20150160668
    Abstract: A voltage regulator circuit arranged to receive a voltage supply signal, and to output a regulated voltage signal is described. The voltage regulator circuit comprises at least one switched mode power supply component selectively configurable to perform regulation of the voltage supply signal, at least one linear voltage regulator component selectively configurable to perform regulation of the voltage supply signal, and at least one controller component.
    Type: Application
    Filed: July 6, 2012
    Publication date: June 11, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Alexandre Pujol, Valerie Bernon-Enjalbert, Mohammed Mansri
  • DIAGNOSTIC DATA GENERATION APPARATUS, INTEGRATED CIRCUIT AND METHOD OF GENERATING DIAGNOSTIC DATA
    Publication number: 20150161759
    Abstract: A diagnostic data generation apparatus for a display controller comprises an underrun detector arranged to monitor, when in use, buffer depletion in order to detect an underrun condition. The underrun condition results from a data feed lag associated with a mismatch between a buffer fill rate and a predetermined output data rate.
    Type: Application
    Filed: April 5, 2012
    Publication date: June 11, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Staudenmaier, Kshitij Bajaj, Mehul Kumar, Steven Mcaslan, Sarthak Mittal
  • SYSTEM ON A CHIP, APPARATUS AND METHOD FOR VOLTAGE RIPPLE REDUCTION ON A POWER SUPPLY LINE OF AN INTEGRATED CIRCUIT DEVICE OPERABLE IN AT LEAST TWO MODES
    Publication number: 20150162818
    Abstract: An apparatus for voltage ripple reduction on a power supply line of an integrated circuit device is provided to be operable in at least two modes. The apparatus includes: one or more clamping devices connectable to the power supply line; a clamp control unit; and a mode change detection unit arranged to monitor an interface of the integrated circuit device for one or more information indicating an upcoming mode change of the integrated circuit device and to provide a mode change signal to the clamp control unit when the one or more information is detected. The clamp control unit is arranged to connect at least one of the one or more clamping devices to the power supply line when receiving the mode change signal.
    Type: Application
    Filed: July 19, 2012
    Publication date: June 11, 2015
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Dan Kuzmin, Sergey Sofer