Abstract: A method for fabricating a semiconductor package is disclosed that includes providing a supply of lead elements, mounting a plurality of the lead elements on a lead frame until a predetermined number of lead elements are placed on the lead frame, and connecting other components on the lead frame to the lead elements.

Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.

Abstract: A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

Abstract: Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.

Abstract: A voltage regulator includes a regulating transistor and a control circuit. The regulating transistor has a first current electrode for providing a regulated voltage, a second current electrode, and a control electrode. The control circuit has an output coupled to the control electrode of the regulating transistor, and an input coupled to the first current electrode of the regulating transistor. The control circuit includes a first inverting gain stage having a first load element, and a second inverting gain stage having a second load element. One of the first or second load elements is characterized as being a diode and the other of the first or second load elements is biased by a bias circuit.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

Abstract: A design verification system automatically identifies coverage of different constraints for a static model of an electronic device. The static model can be employed by a tool, referred to as a solver, that identifies whether the mathematical relationships of the static model can be reconciled, given a set of user-defined constraints that indicate a desired configuration, or range of configurations, of the electronic device. After a solution for a particular set of user-defined constraints has been identified, a constraints adjustment module can identify, based on coverage information generated by the solver, if other sets of user-defined constraints were implicitly solved by the solver. If such other sets were implicitly solved, the adjustments module can mark the sets as solved, such that they will omitted from constraints used for subsequent solutions of the solver.

Abstract: A design verification system verifies an electronic device design based on a static model of the electronic device. The static model is an expression of the relationships between modules of the electronic device design and relationships between the behaviors of those modules that can be expressed as set of logical relationships. The static model does not rely on a time variable, but instead reflects a fixed set of relationships between the electronic device modules and between behaviors of the electronic device modules. The static model can be employed by a solver, that identifies whether or how the mathematical relationships of the static model can be reconciled, given a set of constraints. The solver results can be analyzed to identify whether there are errors in the device design, such as resource conflicts, failure of the design to achieve a desired configuration, and the like.

Abstract: An information processing device comprises a control unit, a hash unit, and a comparison unit. The control unit is arranged to run a program and to store at least flow control information of the program in a call stack. The hash unit is arranged to generate a first hash value by applying a hash function to selected data in response to a first context change of the program, the selected data comprising at least one or more selected items of the call stack, the first context change comprising a termination or interruption of a first process or thread of the program. The control unit is further arranged to start or resume a second process or thread of the program only when the hash unit has generated the first hash value. The hash unit is further arranged to generate a second hash value by re-applying the hash function to the selected data in response to a second context change, the second context change comprising a termination or interruption of the second process or thread.

Abstract: A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region.

Abstract: A method of validating timing issues in a gate-level simulation (GLS) of an integrated circuit design including multiple cells includes running a simulation routine of a behavioral model of the design and obtaining a first simulation result. If there is a possible timing violation at a cell corresponding to a forcing indeterminate value, the simulated output of the cell is forced to a first value and a second simulation result obtained. If this result is negative, a report of apparent timing violations at the cell is generated. If the second simulation result is positive, the output of the cell is then forced to a second value and a third simulation result is obtained. If this result is negative, a report of apparent timing violations at the cell is generated but, if it is positive, a report of no apparent timing violation is generated.

Abstract: A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.

Abstract: A sensor for sensing proximity or touch of an object includes a sensing region, an oscillating signal generator for generating an oscillating signal having an oscillation period, a gating signal generator for generating a gating signal having a gating duration, a controller for controlling the oscillation period or the gating duration and a processor for determining a number N of oscillation periods over the gating duration. The number N is indicative of the object's contact with, or proximity to, the sensing region. The sensor is calibrated by determining an optimal value for the oscillation period or gating duration such that an optimal number N over the gating duration is expected.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.

Abstract: Semiconductor devices are provided with dual passivation layers. A semiconductor layer is formed on a substrate and covered by a first passivation layer (PL-1). PL-1 and part of the semiconductor layer are etched to form a device mesa. A second passivation layer (PL-2) is formed over PL-1 and exposed edges of the mesa. Vias are etched through PL-1 and PL-2 to the semiconductor layer where source, drain and gate are to be formed. Conductors are applied in the vias for ohmic contacts for the source-drain and a Schottky contact for the gate. Interconnections over the edges of the mesa couple other circuit elements. PL-1 avoids adverse surface states near the gate and PL-2 insulates edges of the mesa from overlying interconnections to avoid leakage currents. An opaque alignment mark is desirably formed at the same time as the device to facilitate alignment when using transparent semiconductors.

Abstract: A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid.

Abstract: A semiconductor package has a substrate with a solder mask layer, and upper and lower surfaces. Conductive traces and electrical contacts are formed on the substrate, and vias are formed in the substrate to electrically connect the conductive traces and electrical contacts. A semiconductor die is attached on the upper surface of the substrate. A mold cap is formed on the upper surface of the substrate and covers the die and the conductive traces. The mold cap includes a mold body having clipped corners and extensions that extend from each of the clipped corners. The extensions and clipped corners help prevent package cracking.

Abstract: A semiconductor device package (100) includes a heat spreader (503) formed by depositing a first thin film layer (301) of a first metal on a top surface (150) of a die (110) and to exposed portions of a top surface of an encapsulant (208), depositing a second thin film layer (402) of a second metal on a top surface of the first thin film layer, and depositing a third layer (503) of a third metal on a top surface of the second thin film layer.