Abstract: A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

Abstract: A bandgap voltage reference and voltage regulator system includes a bandgap voltage reference circuit and a voltage regulator circuit that share a single, common amplifier. The amplifier acts as a gain stage for the reference circuit and as an error amplifier for a driver stage of the regulator circuit. The regulator circuit has an input reference generated by the reference circuit, and the reference circuit acts as a load to the driver stage, obviating the need for a bias resistance network. By sharing the amplifier and obviating the need for a resistance network, the area and overall quiescent current of the system are reduced. The system can be implemented in CMOS/BiCMOS technology and is suited for low power applications.

Abstract: A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.

Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure

Abstract: A method of fabricating a sensor device includes forming a plurality of sensor structures on a wafer, covering the plurality of sensor structures with a polymer layer, and dicing the wafer into a plurality of die while each sensor structure remains covered by the polymer layer.

Abstract: An electronic device for proximity detection is described. The electronic device has a first light emitting diode and a control unit. The control unit has a first terminal electrically connected to the anode of the first light emitting diode and a second terminal electrically connected the cathode of the first light emitting diode. The control unit is arranged to operate the first light emitting diode in a plurality of modes, the plurality of modes comprising at least a drive mode and a capacitive sense mode. The control unit is arranged to, in the drive mode, operate the first light emitting diode via the first terminal and the second terminal in forward bias condition for operating the first light emitting diode to generate light. The control unit is arranged to, in the capacitive sense mode, performing a capacitance measurement on at least one terminal of the first terminal and the second terminal.

Abstract: An embodiment of a diode includes a semiconductor substrate, a first contact region having a first conductivity type, a second contact region laterally spaced from the first contact region, and having a second conductivity type, an intermediate region disposed in the semiconductor substrate between the first and second contact regions, electrically connected with the first contact region, and having the first conductivity type, and a buried region disposed in the semiconductor substrate, having the second conductivity type, and electrically connected with the second contact region. The buried region extends laterally across the first contact region and the intermediate region to establish first and second junctions, respectively. The first junction has a lower breakdown voltage than the second junction.

Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.

Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.

Abstract: A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state.

Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. The fabrication method may be carried-out utilizing a preformed panel having a frontside cavity and a backside cavity in which first and second microelectronic devices are positioned, respectively. One or more frontside RDL layers are produced over the frontside of the preformed panel in ohmic contact with or otherwise electrically coupled to the first microelectronic device. Similarly, one or more backside RDL layers are formed over the backside of the preformed panel in ohmic contact with or otherwise electrically coupled to the second microelectronic device. A frontside contact array is produced over the frontside of the preformed panel and electrically coupled to at least the first microelectronic device through the frontside RDL layers. Lastly, the preformed panel is singulated to yield a microelectronic package including a package body in which the first and second microelectronic devices are embedded.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap.

Abstract: In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).

Abstract: An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.

Abstract: A method of forming a dual port pressure sensor includes forming a first opening and a second opening in a flag of a lead frame. An encapsulant is molded to hold the lead frame in which the encapsulant is over a top of the flag and a bottom of the flag is uncovered by the encapsulant. A first opening in the encapsulant is aligned with and larger than the first opening in the flag and a second opening in the encapsulant aligned with the second opening in the flag. A pressure sensor transducer is attached to the bottom of the flag to cover the first opening in the flag, wherein the pressure sensor transducer provides an electrically detectable correlation to a pressure differential based on a first pressure received on its top side and a second pressure received on its bottom side. An integrated circuit is attached to the bottom of the flag. The integrated circuit is electrically coupled to the pressure sensor. A lid is attached to the encapsulant to form an enclosure around the bottom of the flag.

Abstract: A low leakage current transistor (2) is provided which includes a GaN-containing substrate (11-14) covered by a passivation surface layer (17) in which a T-gate electrode with sidewall extensions (20) is formed and coated with a multi-level passivation layer (30-32) which includes an intermediate etch stop layer (31) which is used to define a continuous multi-region field plate (33) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.

Abstract: The disclosure relates to cut-through forwarding module, an integrated circuit, a semiconductor device and a method of receiving and transmitting data frames in a cut-through forwarding mode. The cut-through forwarding module processes received data frames in data blocks. The module comprises a pre-loading unit for storing a first data block of a received data frame. The stored first data block may be pre-loaded by the pre-loading unit in a transmitter unit before a receiver unit receives a subsequent data frame. The processing unit controls the transfer of a first data block to the pre-loading unit and controls the use of a pre-loaded data block as a first data block of a data frame to be transmitted.