Abstract: A device (50) includes a magnetometer (54) adapted to produce an output signal (30) indicative of a sensed magnetic field (38), a second sensor (24), and a processing unit (56) connected to each of the magnetometer and the second sensor. The processing unit is configured to perform operations that include detecting (188) whether the second sensor is in an operational state (94) in which the second sensor is drawing an electric current (82, 86), and when the second sensor is in the operational state, applying (194, 196) a trim parameter (72) to the output signal, the trim parameter canceling at least a portion of a signal error (70) on the output signal, wherein the signal error is generated at the magnetometer in response to the electric current drawn by the second sensor in the operational state.

Abstract: A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

Abstract: The embodiments described herein provide a die crack detector and method that use a conductive trace arranged to at least substantially extend around a perimeter of an integrated circuit die. A one-time programmable element, such as a fuse, is coupled in series with the conductive trace, and a package lead is electrically coupled to both the fuse and another operational element on the integrated circuit die. With the fuse intact the package lead can thus be used to determine a measurement of the conductivity of the conductive trace, with the measurement of conductivity indicative of the presence of a crack on the die. After such testing the fuse can be electrically opened, and the package lead used for normal operation of the device on the packaged die without the conductive trace interfering with this operation.

Abstract: A device includes a power splitter configured to couple to an amplifier having a first path and a second path. The device includes a controller coupled to first and second variable attenuators and first and second adjustable phase shifters. The controller is configured to monitor a phase shift and an output power of each of the first path and second path of the amplifier, and adjust at least one of the first and second variable attenuators and the first and second adjustable phase shifters based upon the phase shift and the output power of each of the first path and second path of the amplifier to modify an input signal to the first path or the second path of the amplifier.

Abstract: A simulation system for testing a simulation of a device against one or more violation rules is described. The simulation system comprises a device simulator for executing the simulation of a device using a device design, a device model and a simulation scenario; and one or more violation monitors, one for each violation rule. Each violation monitor comprises a violation information detector for detecting one or more violations of the respective violation rule during the executing of the simulation and, for each violation, determining information representing the respective violation; a violation score unit for calculating, for each violation of the respective violation rule, a violation score in dependence on the information representing the violation and on a violation rule-specific scheme, and a rule score unit for determining, for the respective violation rule, a rule score from the violation scores of the one or more violations during the simulation.

Abstract: A mold die includes a side wall forming a hollow cavity and opposing first and second axial ends. The side wall has first and second openings respectively at the first and second axial ends. Each of the first and second openings accesses the hollow cavity. A main wall is coupled to the side wall at the first end thereof and spans the first opening. A center of the main wall is aligned with a longitudinal axis of the side wall. The main wall defines a plane oriented generally perpendicularly with respect to the longitudinal axis of the side wall. First and second gates are formed through the main wall to access the hollow cavity. The first and second gates define a first line lying in the plane of the main wall. The center of the main wall is located on the first line between the first and second gates.

Abstract: A system for concurrently testing multiple semiconductor components includes multiple testers, each including a processor and a memory configured to store and execute control signals for completing testing of one of the semiconductor components, a tester side docking board, and a tester communication port. A handler has multiple test sites, each of which is configured to receive one of the semiconductor components, a handler side docking board, and a handler communication port. A controller is located externally from the testers and the handler and is in communication with each of the testers and the handler through the tester and handler communication ports. Communication between each of the testers and the handler occurs through the controller, and each of the testers is connected, via the tester side docking board, to a corresponding one of the semiconductor components through the handler side docking board.

Abstract: The embodiments described herein provide an apparatus and method for separating dies from adhesive tape. In general, these techniques use applied vacuum and one or more channels in an extractor base surface to progressively peel adhesive tape away from the die. When the adhesive tape has been peeled away from the entire die the die can be removed and packaged. Such a technique can reduce the strain the die and thus may reduce the probability of cracks occurring in the die, and is thus particularly applicable to removing adhesive tape from relatively thin dies.

Abstract: In a processing system comprising a plurality of data processors at an integrated circuit die, each data processor has a local debug module. In response to acquiring data trace information based upon a corresponding local filtering criteria, the local debug modules transmit their data trace information to a global resource from each of the local debug modules for further filtering by a common filtering criteria.

Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

Abstract: Protection device structures and related fabrication methods are provided. An exemplary protection device includes a first bipolar junction transistor, a second bipolar junction transistor, a first zener diode, and a second zener diode. The collectors of the first bipolar junction transistors are electrically coupled. A cathode of the first zener diode is coupled to the collector of the first bipolar transistor and an anode of the first zener diode is coupled to the base of the first bipolar transistor. A cathode of the second zener diode is coupled to the collector of the second bipolar transistor and an anode of the second zener diode is coupled to the base of the second bipolar transistor. In exemplary embodiments, the base and emitter of the first bipolar transistor are coupled at a first interface and the base and emitter of the second bipolar transistor are coupled at a second interface.

Abstract: Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1<Rbe<800 Ohms.

Abstract: Embodiments of methods of fabricating a sensor device include attaching first and second die to one another to define first and second cavities in which first and second sensors of the sensor device are disposed, respectively. The second die has an opening in communication with the second cavity. The methods further include obstructing the opening, attaching a third die to the second die. The first cavity is hermetically sealed by attaching the first and second die. The second cavity is hermetically sealed by attaching the third die to the second die.

Abstract: A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) to generate two speculative hit/miss signals. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).

Abstract: A system for imaging a structure of an object is provided. The imaging system includes a degree-of-focus determination module that may comprise logic for taking into account at least one of a first and a second dimension of a topological element of the structure to be imaged. An image processing module of the system may comprise: a control module for controlling a motorized focus driver; a memory for storing images; and said degree-of-focus determination module. The imaging system may comprise: a stage; a motorized focus driver for driving the stage; at least one of microscope optics, a lens, an illumination system; a camera; and an image processing module.

Abstract: An electrostatic discharge (ESD) protection clamp (21, 21?, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21?, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (?Vt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21?, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

Abstract: A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region.

Abstract: Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).

Abstract: Ready-flag circuitry for differential amplifiers. In some embodiments, a semiconductor device may include an amplifier including two inputs, and a ready-flag circuit operably coupled to the amplifier, the ready-flag circuit configured to monitor two or more internal nodes of the amplifier and to produce a signal indicating whether a voltage or current difference between the two inputs has been minimized. In other embodiments, a method may include monitoring, via a ready-flag circuit, a first and a second internal node of a differential amplifier, wherein the differential amplifier is part of a bandgap voltage reference circuit and producing, via the ready-flag circuit, a signal indicating whether an output of the bandgap voltage reference circuit has reached a nominal value.

Abstract: A display controller comprising a blending stage and a blending controller. The blending stage is provided for blending multiple image layers into one display output image and comprises a plurality of input channels for receiving pixel data for the multiple image layers. The blending stage further comprises multiple blenders for combining the pixel data received by at least two input channels of the plurality of input channels. The blending controller is coupled to the blending stage for controlling operation of the blending stage. The blending stage further comprises a controllable switch for coupling an output of at least one blender of the multiple blenders to a display output of the blending stage for regular on-the-fly blending or to an offline blending memory for storing a result of an offline blending task.