Abstract: A charging circuit for at least one bootstrap charge storage element within an inertial load driver circuit is described, the at least one bootstrap charge storage element comprising a first node operably coupled to an output node of at least one switching element of the inertial load driver circuit.

Abstract: An electronic device communicates according to a network protocol that defines data packets, for example EtherCAT. The device has a processor for performing input control on incoming data packets and performing output control on outgoing data packets, and a shared FIFO buffer comprising a multiuser memory. An input unit receives input data, detects the start of a respective data packet, subdivides the data packet into consecutive segments, one segment having a predetermined number of data bytes, and transfers the segment to the FIFO buffer before the next segment has been completely received. The processor accesses, in the input control, the multiuser memory for processing the segment, and, in the output control, initiates outputting the output packet before the corresponding input data packet has been completely received. An output unit transfers the segment from the FIFO buffer, and transmits the segment to the communication medium.

Abstract: A semiconductor device includes a package body, a semiconductor die embedded in the package body and a heat spreader attached to a top surface of the package body and spaced from semiconductor die. The heat spreader may be formed of solder that is melted within a recess in the top surface of the package body.

Abstract: The embodiments described herein can provide improved signal feeding between hybrid couplers and associated transistors. As such, these embodiments can improve the performance of amplifiers and other such RF devices that utilize these components. In one embodiment a device includes a distribution network and a compensation resonator. The distribution network is configured to output a signal through a relatively wide output feedline. This relatively wide output feedline provides distributed signal feeding that can improve signal distribution and performance. The output feedline is coupled to the compensation resonator. In general, the compensation resonator is configured to resonate with the distribution network at the frequency band of the signal. Thus, the distribution network and compensation resonator together can provide improved signal distribution while maintaining performance at the frequencies of interest.

Abstract: Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.

Abstract: A method of making a package substrate having a copper bond pad and a location for receiving a semiconductor die having a remnant of one of a group consisting of HEDP and an HEDP derivative on a top surface of the copper bond pad. The semiconductor die is attached to the substrate. A wirebond connection is attached between the remnant and the semiconductor die.

Abstract: A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analysing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analysing a functional circuit comprising a plurality of timing components is also described.

Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.

Abstract: A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.

Abstract: A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.

Abstract: A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

Abstract: A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.

Abstract: Embodiments of compact micro-electro-mechanical systems (MEMS) devices are provided, as are embodiments of methods for fabricating MEMS devices. In one embodiment, the MEMS device includes a substrate, a movable structure resiliently coupled to the substrate, and an anchored structure fixedly coupled to the substrate. The movable structure includes a first plurality of movable fingers, and a second plurality of movable fingers electrically isolated from and interspersed with the first plurality of movable fingers. The anchored structure includes fixed fingers interspersed with first and second pluralities of movable fingers in a capacitor-forming relationship. First and second interconnects are electrically coupled to the first and second pluralities of movable fingers, respectively.

Abstract: An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Abstract: A transmitter and method for processing a digitally modulated communication signal, which may reduce peak-to-average-power-ratio (PAPR) while maintaining acceptable error rates is disclosed. After subcarrier mapping, a first digital representation of the signal is upsampled into a second digital representation, which is transformed into a first time domain representation. Samples whose magnitudes exceed a magnitude limit are limited to that limit to produce a second time domain representation. The second time domain representation is transformed to a third frequency domain representation, which is downsampled into a fourth frequency domain representation. In addition to the in-band subcarriers, some out-of-band subcarriers adjacent to the frequency band are preserved while the remaining out-of-band subcarriers are eliminated to produce a fifth frequency domain representation.

Abstract: A temperature sensor includes a constant current source and a transistor stack connected to the constant current source. The transistor stack includes a first transistor having a base connected to the constant current source and a collector coupled to a supply voltage. The collector of the first transistor is electrically isolated from the base of the first transistor. The transistor stack includes a second transistor connected to the first transistor. The second transistor has a collector connected to an emitter of the first transistor and has a base connected to the collector of the second transistor. The transistor stack includes an output node disposed between the constant current source and the base of the first transistor. A voltage of the output node is indicative of a temperature.

Abstract: A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.

Abstract: A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

Abstract: A network service dispatcher is provided that transparently navigates network traffic through network service appliances utilizing sub-session connection information generated in accordance with policies pertaining to a client-server session. The network service dispatcher intercepts a first data packet of a new session between two computer systems and generates sub-session connection information that navigates the data packet through one or more network service appliances in a manner transparent to the client or server. In turn, the network service dispatcher utilizes the sub-session connection information to navigate subsequent forward or reverse data packets in the session without performing a policy-based search for each data packet.