Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

Abstract: A method for bonding thin chips to a target substrate is described herein. According to an example method, an adhesive tape is provided with thinned chips attached thereto. The chips are transferred to a carrier substrate by one or more tape-to-tape transfer steps. The carrier is then diced into separate carrier-and-chip assemblies, which can be handled by existing tools designed for handling chips of regular thickness. The fact that the thinning step is separate from the carrier attachment may lead to reduced thickness variation of the chips. The use of tape-to-tape transfer steps allows for attaching either the front or the back side of the chips to the carrier. The use of an individual carrier per chip allows for treating the thinned chip as if it were a standard chip.

Abstract: The present disclosure describes a device for measuring an optical absorption property of a fluid as function of wavelength. The device comprises a broadband light source for emitting light, a plurality of integrated optical waveguides for guiding this light and a light coupler for coupling the emitted light into the integrated optical waveguides such that the light coupled into each integrated optical waveguide has substantially the same spectral distribution. The device also comprises a microfluidic channel for containing the fluid, arranged such as to allow an interaction of the light propagating through each waveguide with the fluid in the microfluidic channel, and a plurality of spectral analysis devices optically coupled to corresponding waveguides—such as to receive the light after interaction with the fluid. The spectral analysis devices are adapted for generating a signal representative of a plurality of spectral components of the light.

Abstract: The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

Abstract: An example embodiment relates to a photonic integrated circuit device and a method for its manufacture. An example device includes a planar detector having at least one photodetector. The device may further include a waveguide layer arranged substantially parallel to the planar detector, the waveguide layer including a first integrated waveguide for guiding a first light signal. A cavity may be formed in the waveguide layer in a region spaced away from the edges of the waveguide layer such as to terminate the first integrated waveguide in that region. A first reflective surface may be provided in the cavity to reflect the first light signal guided by the first integrated waveguide toward a first photodetector of the planar detector.

Abstract: A device (1) for sensing an analyte, the device (1) comprises at least a sample inlet (10) for receiving a sample, affinity probes (111) selected to have a preferential binding to the analyte, a transducer (11) sensitive to a characteristic of the analyte and/or a label attached to the analyte, the transducer not being a FET transducer, and a desalting unit (13) for desalting the received sample.

Abstract: The disclosed technology generally relates to a semiconductor device, and more particularly to a gate all around (GAA) semiconductor device and a method for fabricating the same. In one aspect, a semiconductor device has a vertical stack of nanowires formed on a substrate, wherein the vertical stack of nanowires comprises an n-type nanowire and a p-type nanowire each extending in a longitudinal direction parallel to a main surface of the substrate. The n-type nanowire comprises a first material and the p-type nanowire comprises an inner part having two sides and an outer part at each side of the inner part in the longitudinal direction, wherein one or both of the two outer parts comprises a second material different from the first material. The n-type nanowire and the p-type nanowire each comprises a channel region electrically coupled to respective source and drain regions. The channel region of the p-type nanowire comprises the inner part.

Abstract: The present disclosure relates to directed self-assembly using trench assisted chemoepitaxy. An example embodiment includes a method of forming a pre-patterned structure for directing a self-assembly of a self-assembling material that includes a first and a second component having different chemical natures. The method includes providing an assembly includes a substrate, a layer of pinning material overlying the substrate, and a resist pattern overlaying the layer of pinning material. The method also includes modifying a chemical nature of an exposed part of a top surface of the layer of pinning material. The method further includes removing the resist pattern. In addition, the method includes attaching a neutral layer to the layer of pinning material.

Abstract: A method for immobilizing an analyte-recognizing molecule (1) on a surface (2?) functionalized with chemical groups Y1 suitable for reacting with a chemical group X2 of a coupling molecule (7) to form a reaction product comprising a chemical group Y2 suitable for reacting with the analyte-recognizing molecule (1), the method comprising the steps of: a) Providing the functionalized surface (2?), b) Contacting the functionalized surface (2?) with a solution (6) comprising simultaneously: i) The coupling molecule (7), and ii) The analyte-recognizing molecule (1).

Abstract: The present disclosure is related to a method for detection of defects in a printed pattern of geometrical features on a semiconductor die, the pattern comprising an array of features having a nominal pitch, the method comprising determining deviations from the nominal pitch in the printed pattern, and comparing the printed pattern with another version of the pattern, the other version having the same or similar pitch deviations as the printed pattern. According to various embodiments, the other version of the pattern may a printed pattern on a second die, or it may be a reference pattern, obtained by shifting features of the array in a version having no or minimal pitch deviations, so that the pitch deviations in the reference pattern are the same or similar to the pitch deviations in the printed pattern under inspection.

Abstract: A method for transferring a graphene layer from a metal substrate to a second substrate is provided comprising: providing a graphene layer on the metal substrate, adsorbing hydrogen atoms on the metal substrate by passing protons through the graphene layer, treating the metal substrate having adsorbed hydrogen atoms thereon in such a way as to form hydrogen gas from the adsorbed hydrogen atoms, thereby detaching the graphene layer from the metal substrate, transferring the graphene layer to the second substrate, and optionally reusing the metal substrate by repeating the aforementioned steps.

Abstract: Method of producing one or more transition metal dichalcogenide (MX2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.

Abstract: A method for formation of a transition metal dichalcogenide (TMDC) material layer on a substrate arranged in a process chamber of a molecular beam epitaxy tool is provided. The method includes evaporating metal from a solid metal source, forming a chalcogen-including gas-plasma, and introducing the evaporated metal and the chalcogen-including gas-plasma into the process chamber thereby forming a TMDC material layer on the substrate.

Abstract: According to a first aspect, there is provided a method of holographic wavefront sensing, the method including: receiving a light beam, which has a wavefront to be analyzed, on a transparent, flat substrate, which is provided with a lattice of opaque dots, wherein the substrate is arranged above an image sensor; detecting by the image sensor an interference pattern formed by diffracted light, being scattered by the opaque dots, and undiffracted light of the light beam received by the image sensor; processing the detected interference pattern to digitally reconstruct a representation of a displaced lattice of opaque dots, which would form the interference pattern on the image sensor upon receiving the light with a known wavefront; and comparing the representation of the displaced lattice to a known representation of the lattice of opaque dots on the substrate to determine a representation of the wavefront form of the received light beam.

Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

Abstract: A tunable impedance network includes at least one variable impedance bank comprising a plurality of digitally controlled unit cells each connected from at least a first end to a routing wire. The tunable impedance network is provided with selection means arranged for selecting, based on a desired impedance, a corresponding predetermined digital control signal to be supplied to the variable impedance bank to switch-on a corresponding combination of the unit cells. Between each pair of unit cells in the variable impedance bank, a routing wire section is provided having a respective routing impedance. Each of the predetermined digital control signals is provided for switching-on a combination of unit cells in such a way that the routing impedance of the routing wire section is exploited to fine-tune the actual impedance generated by the variable impedance bank.

Abstract: The disclosed technology generally relates to magnetic devices and more particularly to spin torque majority gate devices, and to methods of operating such devices. In one aspect, a majority gate device comprises a free ferromagnetic layer comprising 3N input zones and an output zone. The output zone has a polygon shape having 3N sides, where each input zone adjoins the output zone. The input zones are arranged around the output zone according to a 3N-fold rotational symmetry, where N is a positive integer greater than 0. The input zones are spaced apart from one another by the output zone. The majority gate device additionally comprises a plurality of input controls, where each of the input zones is magnetically coupled to a corresponding one of the plurality of input controls, where each of the input controls is configured to control the magnetization state of the corresponding input zone.

Abstract: The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack.

Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.

Abstract: An ion sensor for sensing an ion concentration in a bulk solution comprises a reference electrode embedded in an reference electrolyte solution, and a first ion-selective electrode. The ion sensor moreover comprises a second electrode sensitive to the reference ions or to an ion different from the ion to be measured, whereby the second electrode is in direct contact with the bulk solution when the ion sensor is immersed therein. The potential difference between the first electrode and the reference electrode is a measure for the ion concentration in the bulk solution and is corrected with the potential difference between the second electrode and the reference electrode to compensate for the drift of the reference electrode.