Abstract: The present description relates to a readout circuit for digitizing an analog input signal of an imaging device into a digital output. The readout circuit comprises a pixel signal input for providing an analog signal from at least one imaging pixel element, a variable gain amplifier for providing an amplified signal of the analog signal by a gain factor, and a first analog to digital conversion means for quantizing the analog signal into a first digital signal. The circuit further comprises a control means for setting the gain factor of the variable gain amplifier by taking into account the first digital signal, and a second analog to digital conversion means for quantizing the amplified signal into a second digital signal. The circuit also comprises a digital output for outputting a signal determined as function of at least the second digital signal.

Abstract: A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies.

Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly. The IC device or devices in the upper wafer or wafers have contact structures that serve as masks for the etching of the TSV opening. A conformal isolation liner is deposited in the TSV opening, and subsequently removed from the bottom and any horizontal areas in the TSV opening, while maintaining the liner on the sidewalls, followed by deposition of a TSV plug in the TSV opening. The removal of the liner is done without applying a lithography step.

Abstract: An example embodiment may include an interferometer. The interferometer may include a multimode waveguide with an input waveguide optically coupled to a first side of the multimode waveguide, for feeding a light signal to the multimode waveguide. The interferometer may also include a first waveguide at one end optically coupled to a second side of the multimode waveguide, and at the other end terminated by a first waveguide mirror. The interferometer may also include a second waveguide at one end optically coupled to the second side of the multimode waveguide and at the other end terminated by a second waveguide mirror. The multimode waveguide may be adapted to distribute the light signal towards the first and second waveguide mirror via the first waveguide and via the second waveguide.

Abstract: Within examples, a semiconductor device includes a first structure that includes a first doped semiconductor material of a first doping type. The semiconductor device further includes a metal in contact with the first structure, and a second structure that includes a second doped semiconductor material of the first doping type in contact with the first structure. A band off-set for majority charge carriers between the first doped semiconductor material and the second doped semiconductor material is sufficiently large for charge carriers from the second doped semiconductor material to be transferred into the first doped semiconductor material.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor.

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to spin torque devices. In one aspect, a spin torque majority gate device includes a free ferromagnetic layer, a spin mixing layer formed above the free ferromagnetic layer, a non-magnetic tunnelling layer formed above the spin mixing layer, and a plurality of input elements formed above the non-magnetic tunnelling layer, where each input element has a fixed ferromagnetic layer.

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: The present disclosure relates to a telecommunications device. The telecommunications device includes an electrical balance duplexer connected to an output node of a transmission path, an input node of a receive path, an antenna, and a tunable impedance. The electrical balance duplexer is configured to isolate the transmission path from the receive path by tuning the tunable impedance. The telecommunications device also includes a tuning circuit for tuning the tunable impedance. The tuning circuit includes amplitude detectors for measuring voltage amplitudes, phase detectors for measuring voltage phase differences, an impedance sensor for measuring an input impedance of the electrical balance duplexer, and a processing unit operatively connected to the detectors, the impedance sensor, and the tunable impedance. The processing unit is configured to calculate an optimized impedance value. The processing unit is also configured to tune the tunable impedance towards the optimized impedance value.

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

Abstract: A biometric sensor that measures biometric information and a biometric analysis system including the biometric sensor are provided. The biometric sensor may include: a light source configured to emit light toward a region of interest of an object under examination, the light being diffused at the region of interest; a collimator that includes a though-hole and is configured to collimate the diffused light received from the region of interest; and a spectrometer configure to analyze the diffused light transmitted by the collimator.

Abstract: A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying a dual damascene process to a stack of two layers. The bottom layer includes a porous low-k dielectric in which the pores have been filled by a template material. The top layer is a template layer. This stack is obtained by depositing a template layer on top of a porous low-k dielectric and annealing in order to let the template material diffuse into the pores of the low-k layer. At the end of the anneal process, a stack of a pore-filled layer and a template layer is obtained. Vias are etched in the low-k layer and trenches are etched in the template layer. The template pore-filling protects the low-k dielectric during plasma etching, metal barrier deposition and metal deposition.

Abstract: A pixel architecture having an in-pixel amplifier comprising an NMOS transistor and a depletion-mode NMOS load is disclosed. In one aspect, the pixel architecture comprises a pixel core including a pixel photodiode for generating an output signal in accordance with incident light. Further, the in-pixel amplifier is connected to a pixel core to amplify the output signal before it is stored in a column buffer before being read out at output of the pixel architecture. By having an in-pixel amplifier that can be used for amplification of the output signal inside the pixel architecture, a larger output value is obtained which may be stored inside the pixel architecture on a small capacitor with improved signal-to-noise performance. This in-pixel amplification can also improve the quality of stored signals for global shutter operation.

Abstract: The present disclosure relates to an imaging system and a method of generating a depth map. The method comprises generating a first candidate depth map in response to a first pair of images associated with a first textured pattern, generating a second candidate depth map in response to a second pair of images associated with a second textured pattern different from the first textured pattern, determining one of pixels in a same location of the first and second candidate depth maps that is more reliable than the other; and generating a depth map based on the one pixel.

Abstract: The present disclosure relates to a method for emotion-triggered capturing of audio and/or image data by an audio and/or image capturing device. The method includes receiving and analyzing a time-sequential set of data including first physiological data representing a first physiological parameter corresponding to a first person, a second physiological data representing a second physiological parameter corresponding to a second person, and voice audio data including a voice of at least one of the first and the second person, to determine whether a simultaneous change of emotional state of a first person and a second person occurs and transmitting a trigger signal to the capturing device. The present disclosure also relates to a corresponding apparatus and a system comprising the apparatus.

Abstract: The disclosure relates to wavelength-controlled directivity of all-dielectric optical nanoantennas. One example embodiment is an optical nanoantenna for directionally scattering light in a visible or a near-infrared spectral range. The optical nanoantenna includes a substrate. The optical nanoantenna also includes an antenna structure disposed on the substrate. The antenna structure includes a dielectric material having a refractive index that is higher than a refractive index of the substrate and a refractive index of a surrounding medium. The antenna structure includes a structure having two distinct end portions. The antenna structure is asymmetric with respect to at least one mirror reflection in a plane that is orthogonal to a plane of the substrate.

Abstract: An integrated circuit for an imaging device including an array of photo-sensitive areas is disclosed. In one aspect the integrated circuit includes a first multi-layer structure and a second multi-layer structure arranged over a first and a second photo-sensitive area, respectively. The second multi-layer structures each have a bottom and a top reflective structure and a spacer layer arranged therebetween. The spacer layer has a thickness such that the multi-layer structure selectively transmits a narrow range of wavelengths of electro-magnetic radiation. The bottom and top reflective structures include a stack of alternating layers of a first and a second material. Thickness and/or material of the alternating layers of the first multi-layer structure differ from thickness and/or material of the alternating layers of the second multi-layer structure.

Abstract: The present disclosure relates to a method for demodulating a modulated signal and a receiver. The receiver comprises: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. The receiver includes a digitally controlled oscillator comprising: a control input coupled to an output of the comparator and an output of the frequency-offset cancellation block; and an output coupled to the second input of the phase detector.

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: A semiconductor wafer has a silicon single crystal substrate having a top surface and a stack of layers covering the top surface, the stack of layers containing an AlN nucleation layer covering the top surface of the silicon single crystal substrate, wherein the top surface of the silicon single crystal substrate has a crystal lattice orientation which is off-oriented with respect to the {111}-plane, the normal to the top surface being inclined with respect to the <111>-direction toward the <11-2>-direction by an angle ? of not less than 0.3° and not more than 6°, the azimuthal tolerance of the inclination being ±0.1°; and an AlGaN buffer layer which covers the AlN nucleation layer and contains one or more AlxGa1-xN layers, wherein 0<×<1.