Abstract: A method (200) for determining a concentration of an analyte in a fluid or fluid sample, comprises: providing (201) a SERS substrate comprising receptor molecules (107) capable of binding competitor molecules (106); contacting (202) the SERS substrate (102) with a fluid (sample) comprising analyte (108) and such competitor molecules (106); radiating (203) the SERS substrate (102) with a light source while measuring a SERS signal; and determining (205) a concentration of the analyte (108) based on the measured signal level. A corresponding device and system are also provided.

Abstract: The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section from a pattern of parallel fins in a semiconductor structure.

Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

Abstract: The present disclosure is directed to an apparatus and method of batch assembly. The apparatus for batch assembly may include a plurality of spring units, a plurality of handling units, and a control unit. The method of batch assembly may include aligning an array of devices with a plurality of handling units, attaching the array of devices onto the handling units, expanding the handling units so as to expand the array of devices from a first area to a second area, and transferring the array of devices to a destination.

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

Abstract: A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first moveable beam fixed to a first anchor, a first control gate and a second control gate, a first output node against which the first moveable beam can be positioned. The data storage cell also comprises a second nano electromechanical switch comprising a second moveable beam fixed to a second anchor, a third control gate and a fourth control gate. The second moveable beam can be positioned against the first output node. Further, the first nano electromechanical switch and the second nano electromechanical switch are configured for selecting a first or a second state of the data storage cell and are configured for having their moveable beam complementary positioned to the first output node.

Abstract: The present disclosure relates to systems, methods, and sensors configured to characterize a radiation beam. At least one embodiment relates to an optical system. The optical system includes an optical radiation guiding system. The optical radiation guiding system includes a collimator configured to collimate the radiation beam into a collimated radiation beam. The optical radiation guiding system also includes a beam shaper configured to distribute power of the collimated radiation beam over a discrete number of line shaped fields. A spectrum of the collimated radiation beam entering the beam shaper is delivered to each of the discrete number of line shaped fields. The optical system further includes a spectrometer chip. The spectrometer chip is configured to process the spectrum of the collimated radiation beam in each of the discrete number of line shaped fields coming from the beam shaper.

Abstract: The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Abstract: The disclosure is related to a lithographic mask for EUV lithography, to a method for producing the mask, to a method for printing a pattern with the mask, to a stepper/scanner configured to print a pattern with the mask as well as to a computer-implemented method for calculating a deformation of the pattern. The mask comprises an absorber pattern, which is intentionally deformed in the 2-dimensional plane of the EUV mask, with respect to the intended pattern. The deformation of the pattern is based on a previous measurement of the location of multilayer defects on the blank, and calculated so that in the deformed pattern, a maximum of multilayer defects are covered by absorber material. When the pattern is subsequently printed on a semiconductor wafer in a stepper/scanner, the scanner operation is modulated so that the pattern deformation is not reproduced on the wafer.

Abstract: A method for digital driving of an active matrix display with a predetermined frame rate is described. The display contains a plurality of pixels organized in a plurality of rows and a plurality of columns. The method includes representing each of the plurality of pixels of an image to be displayed within a frame by an n-bit digital image code. The method also includes dividing the image frame into sub-frames, which may be of substantially equal duration. Within each sub-frame, the method includes sequentially selecting at least one of the plurality of rows twice. Upon a first selection, a first digital code is written to the selected row and upon a second selection a second digital code is written to the selected row. There is a predetermined time delay between the second selection and the first selection. Digital driving circuitry is also described.

Abstract: A method for forming contact vias includes providing a substrate comprising a plurality of contact structures embedded in a first dielectric layer, the contacts abutting an upper surface of the first dielectric layer. The method also includes providing a second dielectric layer on the upper surface of the first dielectric layer, and providing contact vias in the second dielectric layer by patterning the second dielectric layer at least at positions corresponding to the contact structures, wherein patterning the second dielectric layer comprises using a DSA patterning technique.

Abstract: A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.

Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

Abstract: A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

Abstract: A method for performing a wet treatment of a structure is described in the present disclosure. An example method includes obtaining a structure comprising a first surface, wherein the first surfaces comprises a feature fixed at least at a first end to the first surface from which it protrudes, and wherein a sidewall of the feature faces and is positioned away from a second surface by a gap g, performing a wet treatment of the structure and subsequently, drying the structure, wherein performing the wet treatment comprises rinsing the structure by exposing it to a rinsing liquid comprising water, and exposing the structure, subsequently, to a sequence of liquids.

Abstract: A method for producing a structure including, on a main surface of a substrate, at least one elongated cavity having openings at opposing ends. The method includes providing a substrate having a main surface. On the main surface, a first pair of features are formed that protrude perpendicularly from the main surface. The features have elongated sidewalls and a top surface, are parallel to one another, are separated by a gap having a width s1 and a bottom area, and have a width w1 and a height h1. At least the main surface of the substrate and the first pair of features are brought in contact with a liquid, suitable for making a contact angle of less than 90° with the material of the elongated sidewalls and subsequently the substrate is dried.

Abstract: Embodiments described herein relate to lens-free imaging. One example embodiment may include a lens-free imaging device for imaging a moving sample. The lens-free imaging device may include a radiation source configured to emit a set of at least two different wavelengths towards the moving sample. The lens-free imaging device is configured to image samples for which a spectral response does not substantially vary for a set of at least two different wavelengths. The lens-free imaging device may also include a line scanner configured to obtain a line scan per wavelength emitted by the radiation source and reflected by, scattered by, or transmitted through the moving sample. The line scanner is configured to regularly obtain a line scan per wavelength. Either the radiation source or the line scanner is configured to isolate data of the at least two different wavelengths.

Abstract: The disclosed technology generally relates to integrated circuit devices and methods of forming the same, and more particularly to metal electrodes whose effective work function can be tuned. In one aspect, a method of forming a metal electrode of a semiconductor structure includes providing a semiconductor substrate having at least a region covered with a dielectric. The semiconductor substrate is introduced into a chamber configured for atomic layer deposition (ALD). A metal for the metal electrode is deposited at least on the dielectric by performing an ALD cycle. Performing the ALD cycle includes pulsing a Ti-containing precursor gas followed by pulsing a Ta-containing precursor gas, and further includes pulsing NH3 gas.

Abstract: The disclosure relates to a computer-implemented method and control system for controlling provisioning of a service in a network. A network function specification data structure of a network function of the service is obtained, wherein the network function specification data structure is associated with at least a first network function implementation, e.g. a physical network function implementation, and a second network function implementation, e.g. a virtual network function implementation, for performing the network function of the service. Network service provisioning is controlled comprising selecting the first network function implementation or the second network function implementation of the network function in the network function specification data structure.

Abstract: The disclosure is directed to a method for designing a lithographic mask to print a pattern of structural features, wherein an OPC-based methodology may be used for producing one or more simulated patterns as they would be printed through the optimized mask. A real mask is then produced according to the optimized design, and an actual print is made through the mask. To evaluate the printed pattern and the PW on wafer more accurately, experimental contours are extracted from the CD-SEM measurements of the printed pattern. The verification of the mask is based on a comparison between on the one hand the contour obtained from the printed pattern, and on the other hand the intended pattern and/or the simulated contour. A direct comparison can be made between simulation and experiment, without losing all the pieces of info contained in each single CD-SEM picture.