Abstract: The invention relates to the manufacturing process of a solar cell (1) with back contact and passivated emitter, comprising a dielectric stack (10) of at least two layers consisting of at least a first dielectric layer (11) made of AlOx in contact with a p-type silicon layer (3), and a second dielectric layer (13) deposited on the first dielectric layer (11). Besides, the method of manufacturing comprising a formation step of at least one partial opening (15) preferably by laser ablation into the dielectric stack (10), sparing at least partially the aforementioned first dielectric layer.

Abstract: The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material.

Abstract: A spectral detector includes a plurality of spectral detection units, each of the spectral detection units including an optical signal processor configured to deliver an optical signal incident to the spectral detection unit to an outside of the spectral detection unit, and a resonator configured to modulate a spectrum of an optical signal incident to the optical signal processor by interacting with the optical signal processor, at least some of the resonators of the plurality of spectral detection units having different lengths from each other, and a number of optical signal processors included in each respective spectral detection unit varying according to a length of the resonator included in the respective spectral detection unit.

Abstract: A method of producing a metal-organic framework (MOF) film on a substrate is disclosed, the method comprising providing a substrate having a main surface and forming on said main surface a MOF film using an organometallic compound precursor and at least one organic ligand, wherein each of said organometallic compound precursor and said at least one organic ligand is provided only in vapour phase.

Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio s

Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.

Abstract: An optical device is provided for coupling an external optical signal into a plurality of on-chip photonic sub-circuits provided on a substrate. The optical device comprises: a planar waveguide layer on the substrate; a diverging grating coupler configured to couple the external optical signal to the planar waveguide layer and to thereby create an on-chip diverging optical beam in the planar waveguide layer; and a plurality of channel waveguides formed in the waveguide layer. Each channel waveguide of the plurality of channel waveguides comprises a waveguide transition structure having a waveguide aperture oriented towards the diverging grating coupler. For each channel waveguide of the plurality of channel waveguides the position and the width of the corresponding waveguide aperture and the angle and the shape of the waveguide transition structure are individually selected to capture a predetermined portion of the on-chip diverging optical beam.

Abstract: A method for fabricating Complementary Metal Oxide Semiconductor (CMOS) compatible contact layers in semiconductor devices is disclosed. In one embodiment, a nickel (Ni) layer is deposited on a p-type gallium nitride (GaN) layer of a GaN based structure. Further, the GaN based structure is thermally treated at a temperature range of 350° C. to 500° C. Furthermore, the Ni layer is removed using an etchant. Additionally, a CMOS compatible contact layer is deposited on the p-type GaN layer, upon removal of the Ni layer.

Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.

Abstract: The present disclosure relates to a telecommunications device. The telecommunications device includes an electrical balance duplexer connected to an output node of a transmission path, an input node of a receive path, an antenna, and a tunable impedance. The electrical balance duplexer is configured to isolate the transmission path from the receive path by tuning the tunable impedance. The telecommunications device also includes a tuning circuit for tuning the tunable impedance. The tuning circuit includes amplitude detectors for measuring voltage amplitudes, phase detectors for measuring voltage phase differences, an impedance sensor for measuring an input impedance of the electrical balance duplexer, and a processing unit operatively connected to the detectors, the impedance sensor, and the tunable impedance. The processing unit is configured to calculate an optimized impedance value. The processing unit is also configured to tune the tunable impedance towards the optimized impedance value.

Abstract: A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.

Abstract: A Conductive Bridge Random Access Memory (CBRAM) device comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the conductivity ? of the cation provided by the cation supply electrode in the electrolyte element increases towards the bottom electrode.

Abstract: The present disclosure is related to a method of fabricating a semiconductor device involving the production of at least two non-parallel nano-scaled structures on a substrate. These structures are heated to different temperatures by exposing them simultaneously to polarized light having a wavelength and polarization such that a difference in absorption of light occurs in the first and second nanostructure. In some cases the light is polarized in a plane that is parallel to one of the structures. The present disclosure may provide differential heating of semiconductor structures of different materials, such as Ge and Si fins.

Abstract: A method is provided for forming a feature of a target material on a substrate. The method including: forming a feature of a sacrificial material on the substrate; and forming the feature of the target material by a deposition process during which the feature of the sacrificial material is removed from the substrate by forming a volatile reaction product with a precursor of the deposition process, wherein the sacrificial material is replaced by the target material and the target material is selectively deposited on surface portions of the substrate, which portions were covered by the feature of the sacrificial material, to form the feature of the target material.

Abstract: The present disclosure relates to a delay control circuit arranged for adding delay to a signal. The delay control circuit includes a driver circuit arranged to receive a first signal and to output a second signal. The driver circuit includes a variable load arranged for outputting the second signal by adding delay to the first signal. The delay control circuit also includes a control circuit arranged to receive the first signal and to control the variable load of the driver circuit based on a current state of the first signal and on a control signal indicative of an amount of delay to be added to the first signal in the current state.

Abstract: The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

Abstract: The disclosure relates to a sensor, a system, and a holder arrangement for biosignal activity measurement. One example embodiment includes a sensor module for brain activity measurement. The sensor module includes a main electrode base. The sensor module also includes a plurality of pins protruding from the main electrode base. The plurality of pins is arranged such that, when applied on a subject, the pins make contact with skin of the subject or are in close proximity with the skin of the subject. The main electrode base comprises electronic circuitry for near infrared spectroscopy (NIRS) measurements and electronic circuitry for electroencephalography (EEG) measurements, both connected to the plurality of pins. The plurality of pins includes electrically conductive pins. The plurality of pins also includes at least one source waveguide pin configured for light emitting purposes or at least one detector waveguide pin configured for light detection purposes.

Abstract: The present disclosure relates to a method for demodulating a modulated signal and a receiver. The receiver comprises: a phase detector with a first and second input, the first input being adapted to receive a modulated input signal; a comparator comprising an input coupled to an output of the phase detector; a frequency-offset cancellation block comprising an input coupled to an output of the comparator. The receiver includes a digitally controlled oscillator comprising: a control input coupled to an output of the comparator and an output of the frequency-offset cancellation block; and an output coupled to the second input of the phase detector.

Abstract: An amplifier circuit, a voltage sensing apparatus, and an amplification method are disclosed. The amplifier circuit comprises (1) an input stage comprising a first set of transistors to which an input signal to be amplified is applied, the transistors of the first set comprising a semiconductor body, and (2) a processing stage comprising a second set of transistors for processing the signal from the input stage and generating an output signal. The transistors of the first set have a thicker gate oxide than the transistors of the second set, and are therefore suitable for higher voltage operation. The first and second sets of transistors are supplied by the same voltage supply of the amplifier circuit. The semiconductor body of the first set of transistors is connected to a reference potential to lower the threshold voltage.

Abstract: A method for stimulating a human leg, a stimulation system, and a garment including the stimulation system are disclosed. The method comprises: measuring, by a measuring unit, an electrical characteristic indicative of a physiological condition in a portion of the leg via a subset of skin electrodes comprised in a plurality of skin electrodes integrated in a leg part of a garment arranged to be worn about at least a part of the human leg; determining, by evaluating the measured electrical characteristic, if the portion of the leg is to be stimulated; and if it is determined that the portion is to be stimulated, applying a stimulation via a subset of stimulation units, comprised in a plurality of stimulation units being arranged in the leg part of the garment, such that the portion of the leg is stimulated. A stimulation system and a garment comprising such as stimulation system are also disclosed.