Abstract: The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor, and a differential sense amplifier. The first transistor is a Vt-modifiable n-channel transistor and the second transistor is a Vt-modifiable p-channel transistor, each transistor having first and second main electrodes. The first main electrodes of the first and second transistors are connected together. The differential sense amplifier is connected to the second main electrodes of the first and the second transistor. The differential sense amplifier is adapted for sensing the current difference between the first transistor and the second transistor.

Abstract: The disclosure relates to systems and methods for acquisition of biosignals with motion sensor-based artifact compensation. One example embodiment is a system for acquisition of biosignals from a subject. The system includes at least one biosensor worn over a first location of a body part of the subject configured for biosignal measurement and providing a measured biosignal. The system also includes a plurality of inertial motion sensors worn over a plurality of locations of the body part of the subject. Each of the inertial motion sensors is configured for providing a motion vector signal. The system further includes a biosignal adaptation unit configured for receiving and adapting the measured biosignal. In addition, the system includes a motion estimation unit. Further, the system includes a digital filter unit. At least one of the plurality of inertial motion sensors is mechanically connected to the at least one biosensor.

Abstract: A device and method for manufacturing a Si-based high-mobility CMOS device is provided.

Abstract: A system for hand gesture detection is provided, comprising: a wrist wear adapted to be worn about a wrist of a user of the system and including a set of skin electrodes adapted to face the wrist; an impedance measurement circuit adapted to measure at least a first impedance in a first portion of the wrist and a second impedance in a second portion of the wrist which second portion is circumferentially displaced in relation to said first portion, wherein the first impedance is measured via a first electrode group including four skin electrodes of said set of skin electrodes and the second impedance is measured via a second electrode group including four skin electrodes of said set of skin electrodes, and a processing circuit adapted to detect a hand gesture of the user based on the first and the second impedance measured by the impedance measurement circuit.

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method include epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

Abstract: The disclosure relates to a method of fabricating an enhancement mode Group III-nitride HEMT device and a Group III-nitride structure fabricated therefrom. One example embodiment is a method for fabricating an enhancement mode Group III-nitride HEMT device. The method includes providing a structure. The structure includes a substrate having a main surface. The structure also includes a layer stack overlying the main surface. Each layer of the layer stack includes a Group III-nitride material. The structure further includes a capping layer on the layer stack. The method also includes forming a recessed gate region by removing, in a gate region, at least the capping layer by performing an etch process, thereby exposing a top surface of an upper layer of the layer stack. The method further includes forming a p-type doped GaN layer in the recessed gate region and on the capping layer by performing a non-selective deposition process.

Abstract: The present invention provides a method to analyze or identify a cell. The method comprises: providing a cell, stimulating the cell with a stimulant thereby modifying a cell membrane impedance of the cell, monitoring the cell membrane impedance of the cell and identifying the cell based on the monitored cell membrane impedance. A corresponding device is also provided.

Abstract: The present disclosure relates to a method (100) for depositing a layer on a III-V semiconductor substrate, in which this method comprises providing (102) a passivated III-V semiconductor substrate comprising a III-V semiconductor surface which has a surface passivation layer provided thereon for preventing oxidation of said III-V semiconductor surface. The surface passivation layer comprises a self-assembled monolayer material obtainable by the reaction on the surface of an organic compound of formula R-A, wherein A is selected from SH, SeH, TeH and SiX3. X is selected from H, Cl, O—CH3, O—C2H5, and O—C3H2, and R is a hydrocarbyl, fluorocarbyl or hydrofluorocarbyl comprising from 5 to 20 carbon atoms. The method further comprises thermally annealing (107) the III-V semiconductor substrate in a non-oxidizing environment such as to decompose the self-assembled monolayer material, and depositing (108) a layer on the III-V semiconductor surface in the non-oxidizing environment.

Abstract: A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (tf) of 100 ns or less and a pulse amplitude (If) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (ts) of 100 ns or less and a pulse amplitude (Is) equal to or larger than the forming current pulse amplitude (If).

Abstract: A biopotential signal acquisition system, comprising: a first active electrode including an integrated pre-amplifier and an analogue to digital converter; a second active electrode including an integrated pre-amplifier and an analogue to digital converter, wherein the second active electrode has variable gain; a test signal generator for generating a test signal at a test frequency and coupling the test signal to the first and/or second active electrodes; and a digital signal processor configured to: process the digital outputs of the first and second active electrodes to derive a gain control signal based on a difference between the first and second active electrode outputs at the test frequency, and apply the gain control signal to the second active electrode. The disclosure also relates to an electronic circuit or device and a biopotential signal acquisition method.

Abstract: A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.

Abstract: Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells are disclosed. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.

Abstract: A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.

Abstract: The present disclosure relates to a method for pattern formation on a substrate. An example embodiment includes a method for pattern formation. The method includes providing a photoresist layer on a composite substrate. The method also includes patterning the photoresist layer by lithography to define a plurality of parallel stripe photoresist structures. The method further includes providing a block copolymer on and along the composite substrate, in between the parallel stripe photoresist structures. The block copolymer includes a first component and a second component. The method additionally includes subjecting the block copolymer to predetermined conditions to cause phase separation of the first component and the second component. In addition, the method includes performing a sequential infiltration synthesis process. Still further, the method includes selectively removing the parallel stripe photoresist structures. Additionally, the method includes defining a core stripe structure.

Abstract: A spectral detector includes a plurality of spectral detection units, each of the spectral detection units including an optical signal processor configured to deliver an optical signal incident to the spectral detection unit to an outside of the spectral detection unit, and a resonator configured to modulate a spectrum of an optical signal incident to the optical signal processor by interacting with the optical signal processor, at least some of the resonators of the plurality of spectral detection units having different lengths from each other, and a number of optical signal processors included in each respective spectral detection unit varying according to a length of the resonator included in the respective spectral detection unit.

Abstract: The present disclosure discloses an apparatus and method for monitoring performance of an integrated circuit. The apparatus includes a delay line, which receives a pulse signal. The delay line has a controllable, variable length and propagates the pulse signal through a set length. The apparatus also includes a comparator, which receives the propagated pulse signal from the delay line and a clock signal, the comparator being arranged to determine whether the received signal is received early or late. The apparatus also includes a feedback loop, which receives input from the comparator for dynamically increasing or decreasing the set length of the delay line in dependence of the determination by the comparator. The apparatus determines a speed of the integrated circuit based on a determination by the comparator that the signal from the delay line closely matches the clock signal.

Abstract: The present disclosure is related to a method for detection of defects in a printed pattern of geometrical features on a semiconductor die, the pattern comprising an array of features having a nominal pitch, the method comprising determining deviations from the nominal pitch in the printed pattern, and comparing the printed pattern with another version of the pattern, the other version having the same or similar pitch deviations as the printed pattern. According to various embodiments, the other version of the pattern may a printed pattern on a second die, or it may be a reference pattern, obtained by shifting features of the array in a version having no or minimal pitch deviations, so that the pitch deviations in the reference pattern are the same or similar to the pitch deviations in the printed pattern under inspection.

Abstract: The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

Abstract: In a first aspect, a micro-fluidic device is presented, comprising: a micro-fluidic channel having an inner surface; a sensing region inside the micro-fluidic channel configured for adsorbing at least one analyte, the sensing region comprising a plurality of pillars positioned along the length of the inner surface of the micro-fluidic channel wherein the plurality of pillars are configured for creating an electromagnetic field localization thereby making the sensing region suitable for sensing plasmonic or surface enhanced Raman signals when irradiated; characterized in that: the plurality of pillars are further configured for creating a capillary action in the micro-fluidic channel when a fluid sample is present in the micro-fluidic channel.

Abstract: A carrier-depletion based silicon waveguide resonant cavity modulator includes a silicon waveguide based resonant cavity. The resonant cavity includes an optical modulation section and an optical power monitoring section. The optical power monitoring section includes an integrated lateral PIN diode including a doping compensated I region having a high defect density and a low net free carrier concentration. The doping compensated I region may be formed by performing a P-type implantation step and an N-type implantation step with overlapping ion implantation windows.