Abstract: The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

Abstract: An optical semiconductor device comprises, on a substrate, a fin of diamond-cubic semiconductor material and, at the base of the fin, a slab of that semiconductor material, in a diamond-hexagonal structure, that extends over the full width of the fin, the slab being configured as an optically active material. This semiconductor material can contain silicon. A method for manufacturing the optical semiconductor device comprises annealing the sidewalls of the fin, thereby inducing a stress gradient along the width of the fin.

Abstract: A loader work machine has a base frame including a cabin; a loader work apparatus attached to the base frame; and two traveling apparatuses supporting the base frame, and including: a track frame connected to the base frame; a drive wheel driving a traveling belt; front and rear idlers arranged in a front-back direction below the drive wheel and supported by the track frame; and one or more track rollers arranged between the front and rear idlers and supported by the track frame, the traveling belt stretched around the drive wheel, idlers, and track rollers. The base frame includes: a lower frame connected to two track frames and interposed between the traveling apparatuses; an upper frame provided with the loader work apparatus; and a slewing apparatus connecting the upper and lower frames. The upper frame connected to the lower at an upper frame bottom surface being above the traveling belts.

Abstract: A microfluidic chip for use in multiplexed analysis of samples is described. The microfluidic chip comprises a plurality of sensing chambers and further comprises at least a first fluid supply channel for providing a first fluid and a plurality of microfluidic channels. These are in fluid communication with at least one sensing chamber and with the first fluid supply channel for delivery of said first fluid to the at least one sensing chamber. The microfluidic channels are branching off from the supply channel in the neighborhood of the sensing chamber that can be provided with the first fluid through the microfluidic channel. The different channels thus form a tree-like delivery distribution system for supplying the first fluid to said plurality of sensing chambers.

Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

Abstract: The present disclosure relates to devices and methods for non-invasive measuring of analytes. At least one embodiment relates to a wearable system for non-invasive measuring of a concentration of an analyte in skin tissue. The wearable system includes an integrated circuit that includes a first optical unit. The first optical unit includes a Raman spectrometer. The first optical unit also includes an OCT spectrometer and an interferometer optically coupled to the OCT spectrometer or an infrared (IR) spectrometer. The first optical unit additionally includes a light coupler. The wearable system further includes a first light source for performing Raman spectroscopy. The wearable system additionally includes a second light source for performing OCT spectroscopy or IR spectroscopy. Still further, the wearable system includes read-out electronics to determine an optical model of the skin tissue based on the spectroscopic data and to determine the concentration of the analyte.

Abstract: The present disclosure relates to a device for analyzing a fluid sample. In one aspect, the device includes a fluidic substrate that comprises a micro-fluidic component embedded in the fluidic substrate configured to propagate a fluid sample via capillary force through the device and a means for providing a fluid sample connected to the micro-fluidic component. The device also includes a lid attached to the fluidic substrate at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component. The fluidic substrate may be a silicon fluidic substrate and the lid may be a CMOS chip. In another aspect, embodiments of the present disclosure relate to a method for fabricating such a device, and the method may include providing a fluidic substrate, providing a lid, and attaching, through a CMOS compatible bonding process, the fluidic substrate to the lid to close the fluidic substrate at least partly.

Abstract: A variable capacitor circuit is disclosed. The variable capacitor circuit includes a plurality of MOS capacitors, each MOS capacitor being implemented by a MOS transistor with the gate terminal connected to a first voltage signal and with the drain terminal shorted with the source terminal and connected to a second voltage signal, said MOS capacitors being connected in parallel through the gate terminal connected to the first voltage signal, and being operated in a cut-off region in which the equivalent capacitance of each MOS capacitor remains substantially constant for variations of the first voltage signal.

Abstract: The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.

Abstract: The disclosed technology relates generally to probe configurations, and more particularly to probe configurations and methods of making probe configurations that have a diamond body and a diamond layer covering at least an apex region of the diamond body. In one aspect, a method of fabricating a probe configuration includes forming a probe tip. Forming the probe tip includes providing a substrate and forming a recessed mold into the substrate on a first side of the substrate, wherein the recessed mold is shaped to form a probe body having an apex region. Forming the probe tip additionally includes forming a first diamond layer on the substrate on the first side, wherein forming the first diamond layer includes at least partially filling the recessed mold with the first diamond layer such that a probe body having an apex region is formed in the recessed mold.

Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.

Abstract: The disclosure relates to a method for forming a conformal coating on a substrate having a topography presenting a relief. One method of the disclosure includes setting the temperature of the substrate within the range 140-275° C., and coating an aqueous solution including a sol-gel precursor on said substrate. The disclosure also relates to a method for fabricating a battery, a capacitor, a catalyst, a photovoltaic cell or a sensor using such a method, and to an aqueous solution for use in such a method.

Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.

Abstract: An all-digital phase-locked loop (AD-PLL) and related methods and computer readable medium are provided. The AD-PLL comprises a reference phase generator for receiving a digital signal and splitting the digital signal into an integer part and a fractional part, an estimator block for estimating a control signal, and a digital-to-time converter for receiving the estimated control signal and a reference clock signal and for deriving a delayed reference clock signal. The AD-PLL also includes a time-to-digital converter for receiving the delayed reference clock signal and a desired clock signal phase, and for deriving a fractional phase error. The estimator block receives the fractional phase error and determines the estimated control signal by correlating the fractional phase error with the fractional part, yielding a correlated signal, multiplying the correlated signal with its absolute value, and integrating the outcome of the multiplying to obtain the estimated control signal.

Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P<N, and P of the M outputs, P<M, via paths of connected and activated segments of the segmented bus network. The segments are linked by segmentation switches. The N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches.

Abstract: The present disclosure relates to semiconductor devices for detecting fluorescent particles. At least one embodiment relates to an integrated semiconductor device for detecting fluorescent tags. The device includes a first layer, a second layer, a third layer, a fourth layer, and a fifth layer. The first layer includes a detector element. The second layer includes a rejection filter. The third layer is fabricated from dielectric material. The fourth layer is an optical waveguide configured and positioned such that a top surface of the fourth layer is illuminated with an evanescent tail of excitation light guided by the optical waveguide when the fluorescent tags are present. The fifth layer includes a microfluidic channel. The optical waveguide is configured and positioned such that the microfluidic channel is illuminated with the evanescent tail. The detector element is positioned such that light from activated fluorescent tags can be received.

Abstract: In one example, the method disclosed herein includes, among other things, forming a sacrificial structure around a plurality of stacked substantially un-doped nanowires at a location that corresponds to the channel region of the device, performing a selective etching process through a cavity to remove a second plurality of nanowires from the channel region and the source/drain regions of the device while leaving a first plurality of nanowires in position, and forming a metal conductive source/drain contact structure in each of the source/drain regions, wherein each of the metal conductive source/drain contact structures is positioned all around the first plurality of nanowires positioned in the source/drain regions.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract: A spectroscopy system includes detectors configured to obtain detection spectrums of respective detection areas that are located at different positions of an object; and an information processor configured to obtain a target spectrum of a target area by using position information of the detection areas and the detection spectrums obtained by the detectors.

Abstract: The disclosed technology relates to a magnetic memory device. In one aspect, the device includes a first electrode comprising a conductive pillar formed over the substrate and elongated in a vertical direction crossing a lateral surface of the substrate. The device additionally includes a second electrode extending in a lateral direction crossing the first direction, where the second electrode intersects the first electrode. The device additionally includes a magnetic tunnel junction (MTJ) formed at an intersection between the first electrode and the second electrode, where the MTJ continuously surrounds the first electrode. The MTJ includes a reference layer continuously surrounding the pillar of the first electrode, a free layer continuously surrounding the free layer, and a dielectric tunnel barrier interposed between the reference layer and the free layer.