Abstract: A substrate is described that is suitable for surface enhanced optical detection. The substrate comprises an electrically conductive layer The substrate further comprises at least one nanoparticle comprising an electrically conductive portion. The electrically conductive portion may provide an opening to an underlying material. Such at least one nanoparticles may be a nanoring, a nanodisc, or a non-spherical nanoshell. The substrate further comprises a dielectric spacer for spacing the electrically conductive layer from the at least one nanoparticles. The dielectric spacer is a dielectric material substantially only present under the at least one nanoparticle, leaving the electrically conductive layer uncovered from dielectric material at positions away from the nanoparticles. The at least one nanoparticle and the dielectric spacer are interfaced along a first major surface and the at least one nanoparticle comprises an upstanding surface not in line with an upstanding surface of the dielectric spacer.

Abstract: Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.

Abstract: A semiconductor device includes a Schottky diode and a High Electron Mobility Transistor (HEMT) formed on a III-nitride stack. The III-nitride stack includes at least a lower and an upper III-nitride layer forming a heterojunction therebetween, so that a 2-dimensional electron gas (2DEG) layer may be formed in the lower layer. The 2DEG layer serves as a charge carrier for the diode and the HEMT. A doped III-nitride layer may be present between a portion of the anode of the diode and the III-nitride stack, and the portion may be located between the diode's Schottky junction and the cathode. A further layer of doped III-nitride material may be present between the gate electrode of the HEMT and the III-nitride stack. The thickness of the III-nitride layers is not equal, so that the turn-on voltage of the diode and the threshold voltage of the HEMT may be tuned according to specific requirements. The disclosure also involves a method of producing such a semiconductor device.

Abstract: A method and an electronic readout circuit for measuring a capacitance of a MEMS sensor are disclosed. In one aspect, the readout circuit includes: an input stage for receiving a first signal from the sensor and for presenting a second signal; a charge amplifier stage for amplifying and integrating the second signal; and a control logic for controlling the readout circuit according to a predefined timing relation synchronized to actuation voltages applied to the sensor for generating the first signal. The readout circuit may further includes a first switching unit for applying a first reference voltage to the sensor and a second switching unit for applying the second signal to the charge amplifier stage, wherein the first and the second switching units are controlled according to the predefined timing relation such that a plurality of the second signals are accumulated.

Abstract: A digital front-end circuit is disclosed. In one aspect, the circuit includes a filtering block for filtering received data. The filtering block has a first filter branch for filtering the received data in a first frequency band and a second filter branch for filtering the received data in a selected second frequency band. The second filter branch is in parallel with the first filter branch, is programmable and includes a block for resampling the received data. The front-end circuit also includes a circuit for performing synchronization and spectrum sensing on the received data, which is in connection with the output of the filtering block. The front-end circuit also includes a controller block for controlling the filtering block and the synchronization circuit.

Abstract: An analog signal processor (ASP) application-specific integrated circuit (ASIC) is disclosed. The ACIS can be used for remotely monitoring ECG signals of a subject that has reduced power consumption. In one aspect, the ASIC performs the functions of: ECG signal extraction with high resolution using ECG readout channel, feature extraction using a band-power extraction channel, adaptive sampling the ECG signals using an adaptive sampling analog-to-digital converter, and impedance monitoring for signal integrity using an impedance monitoring channel. These functions enable the development of wireless ECG monitoring systems that have significantly lower power consumption but are more efficient that predecessor systems. In one embodiment, the ASP ASIC consumes 30 ?W from a 2V supply with compression provided by adaptive sampling providing large reductions in power consumption of a wireless ECG monitoring system of which the ASP ASIC forms a part.

Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.

Abstract: The present invention relates generally to testing of interconnects in a semiconductor die, and more particularly to testing of semiconductor chips that are three-dimensionally stacked via an interposer. In one aspect, a method for testing an interconnect in a semiconductor die comprises providing the semiconductor die, which includes a plurality of electrical contact elements formed at one or more surfaces of the semiconductor die, at least one interconnect-under-test disposed between a first electrical contact element and a second electrical contact element, and an electrical component electrically coupled between the interconnect-under-test and at least one third electrical contact element.

Abstract: A method for managing the operation of an electronic system by taking into account various cost constraints of the system is disclosed. In one aspect, the method includes selecting a working mode for a plurality of tasks in a pro-active way using predictive control mechanism while guaranteeing hard real time constraints. The system is operated at the selected working mode for the corresponding tasks.

Abstract: Disclosed herein are methods and devices for monitoring a heartbeat. In one embodiment, the device may comprise a sensor package mountable over a pulse location of a user. The sensor package may include a first sensor element configured to sense at least one signal at the pulse location and to provide a first output signal comprising a heart pulse signal and a first set of noise artifacts, a second sensor element configured to sense at least one signal at the pulse location and to provide a second output signal indicative of a second set of noise artifacts, and a mechanically isolating material located between the first sensor element and the second sensor element. The device may further comprise processing circuitry connected to the sensor package and configured to extract the heart pulse signal from the first output signal based on the first output signal and the second output signal.

Abstract: The disclosed technology generally relates photovoltaic devices, and more particularly to methods of fabricating heterojunction interdigitated back contact photovoltaic cells having interdigitated emitter regions and back surface field regions.

Abstract: A two-axes MEMS magnetometer includes, in one plane, a freestanding rectangular frame having inner walls and four torsion springs, wherein opposing inner walls of the frame are contacted by one end of only two torsion springs, each torsion spring being anchored by its other end, towards the centre of the frame, to a substrate. In operation, the magnetometer measures the magnetic field in two orthogonal sensing modes using differential capacitance measurements.

Abstract: A MEMS switch is provided wherein contact force sufficient to make a contact having low contact resistance is maintained after contact-formation to maintain low contact resistance at the signal transmission contact in “on” state. Provided is a MEMS switch 100 including a first electrode 101, a second electrode 104 opposed to and separated from the first electrode, a third and a fourth electrodes 1021 and 1022, wherein electrical contact is made between the electrodes 101 and 104 by electrostatic force generated between the electrode 101 and the electrodes 1021, 1022, and a bump which can form the contact between the electrode 101 and the electrode 1021 and/or 1022 is provided on the electrode 101, and a gap is formed between the electrode 101 and the electrode 1021 and/or 1022 when the electrical contact is made, and control signals are input to the electrodes 1021 and 1022 independently.

Abstract: A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

Abstract: The present invention provides a method to analyze or identify a cell. The method comprises: providing a cell, stimulating the cell with a stimulant thereby modifying a cell membrane impedance of the cell, monitoring the cell membrane impedance of the cell and identifying the cell based on the monitored cell membrane impedance. A corresponding device is also provided.

Abstract: A spectral camera having an objective lens, an array of lenses for producing optical copies of segments of the image, an array of filters for the different optical channels and having an interleaved spatial pattern, and a sensor array to detect the copies of the image segments is disclosed. Further, detected segment copies of spatially adjacent optical channels have different passbands and represent overlapping segments of the image, and detected segment copies of the same passband on spatially non-adjacent optical channels represent adjacent segments of the image which fit together. Having segments of the image copied can help enable better optical quality for a given cost. Having an interleaved pattern of the filter bands with overlapping segments enables each point of the image to be sensed at different bands to obtain the spectral output for many bands simultaneously to provide better temporal resolution.

Abstract: A spectral camera for producing a spectral output is disclosed. The spectral camera has an objective lens for producing an image, an optical duplicator, an array of filters, and a sensor array arranged to detect the filtered image copies simultaneously on different parts of the sensor array. Further, a field stop defines an outline of the image copies projected on the sensor array. The filters are integrated on the sensor array, which has a planar structure without perpendicular physical barriers for preventing cross talk between each of the adjacent optical channels. The field stop enables adjacent image copies to fit together without gaps for such barriers. The integrated filters mean there is no parasitic cavity causing crosstalk between the adjacent image copies. This means there is no longer a need for barriers between adjacent projected image copies, and thus sensor area can be better utilized.

Abstract: Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget.

Abstract: A III-nitride device is provided comprising a semiconductor substrate; a stack of active layers on the substrate, each layer comprising a III-nitride material; a gate, a source and a drain contact on the stack, wherein a gate, a source and a drain region of the substrate are projections of respectively the gate, the source and the drain contact in the substrate; and a trench in the substrate extending from a backside of the substrate (side opposite to the one in contact with the stack of active layers) to an underlayer of the stack of active layers in contact with the substrate, the trench completely surrounding the drain region, being positioned in between an edge of the gate region towards the drain and an edge of the drain region towards the gate and having a width such that the drain region of the substrate is substantially made of the semiconductor material.

Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.