Abstract: A semiconductor device is described advantageously making use of the interposer principle. The semiconductor device comprises at least one semiconductor die, a window substrate being an inorganic substrate comprising at least one window-shaped cavity for mounting the at least one semiconductor die, the window substrate having interconnect structures. Furthermore, the at least one semiconductor die is positioned inside the at least one cavity and is connected to the interconnect structures, providing connections to another level of assembly or packaging of the semiconductor device. The invention also relates to a method of manufacturing such a semiconductor device.

Abstract: In an aspect of the disclosure, a stimulation device includes a probe attached to a first support. The probe includes at least one grating coupler for coupling light into the probe. The device further includes at least one optical source for providing an optical stimulation signal mounted on a second support, and at least one means for detachably attaching the first support to the second support. The position of the at least one optical source is aligned with the position of the at least one grating coupler to allow light emitted from the at least one optical source to be received by the at least one grating coupler.

Abstract: A method is provided for producing a LED device, comprising a stack of layers comprising a light producing layer the light producing layer not being the top or bottom layer of the stack, wherein a layer at the top or bottom of the stack is subjected to a texturization aimed at enhancing the light extraction efficiency of the LED, wherein the texturization comprises the step of producing on the top or bottom surface a plurality of surface features, the surface features being arranged according to a pattern defined by starting from a regular pattern of features and subjecting each feature of the regular pattern to a deviation from the location in the regular pattern, the deviation being in a random direction and/or having a random amplitude. According to another embodiment, a random deviation is applied to one or more dimensions of the features in the regular pattern.

Abstract: A method for manufacturing interdigitated back contact photovoltaic cells is disclosed. In one aspect, the method includes providing on a rear surface of a substrate a first doped layer of a first dopant type, and providing a dielectric masking layer overlaying it. Grooves are formed through the dielectric masking layer and first doped layer, extending into the substrate in a direction substantially orthogonal to the rear surface and extending in a lateral direction underneath the first doped layer at sides of the grooves. Directional doping is performed in a direction substantially orthogonal to the rear surface, thereby providing doped regions with dopants of a second dopant type at a bottom of the grooves. Dopant diffusion is performed to form at the rear side of the substrate one of the emitter regions and back surface field regions between the grooves and the other at the bottom of the grooves.

Abstract: A method for producing a GaNLED device, wherein a stack of layers comprising at least a GaN layer is texturized, is disclosed. The method involves (i) providing a substrate comprising on its surface said stack of layers, (ii) depositing a resist layer directly on said stack, (iii) positioning a mask above said resist layer, said mask covering one or more first portions of said resist layer and not covering one or more second portions of said resist layer, (iv) exposing said second portions of said resist layer to a light source, (v) removing the mask, and (vi) bringing the resist layer in contact with a developer comprising potassium, wherein said developer removes said resist portions that have been exposed and texturizes the surface of at least the top layer of said stack by wet etching said surface, in the areas situated underneath said resist portions that have been exposed.

Abstract: The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.

Abstract: An example micro-fluidic device includes a micro-fluidic channel having an inner surface and a plurality of pillars positioned along the inner surface. The device further includes a plurality of power supplies connected to the pillars. Another example micro-fluidic device includes a micro-fluidic channel having an inner surface and a plurality of pillars positioned along the inner surface. The device further includes a power supply. The pillars are grouped into at least two groups of pillars, each group of pillars including at least two pillars, and all pillars of at least one group of pillars are connected to the power supply. In another example, a sensing system for detecting bioparticles includes a micro-fluidic device, wherein a surface of each pillar comprises functionalized plasmonic nanoparticles or functionalized SERS nanoparticles, a radiation source for radiating the micro-fluidic device, and a detector for detecting SERS signals or surface plasmon resonance.

Abstract: The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.

Abstract: A device including a sample and hold circuit for providing a signal related to an input analogue current signal, by sampling the input analogue current signal and integrating it on capacitive means, thereby charging the capacitive means to a charge value. The capacitive means being configurable to dynamically change its effective capacitance value in order to shape a voltage signal present on the capacitive means such that the charge value remains unchanged. The device also including an analogue-to digital conversion (ADC) and control circuit arranged for performing an ADC of the at least one related signal at the output of the sample and hold circuit into an output digital signal, the ADC and control circuit including successive approximation ADC means for considering the value of the voltage signal on the capacitive means and converting the charge value present in the capacitive means into the digital output signal.

Abstract: The present invention relates to a method (1) for creating a diamond structure (38) on a substrate (31). This method comprises the steps of providing (2) a substrate (31), providing (3) a mold (25) on the substrate (31), providing (4) a diamond seed solution (34) in the mold (25), and removing (6) the mold (25) such that a diamond structure (38) remains on the substrate (31).

Abstract: A method includes providing a dummy gate structure on a substrate. The dummy gate structure includes a gate dielectric layer and a dummy gate electrode layer, and is laterally defined by inner sidewalls of a set of spacers. The method also includes laterally embedding the dummy gate structure, removing the dummy gate electrode, and providing a final gate electrode layer in between the inner sidewalls of the set of spacers. Providing the final gate electrode layer further includes providing a diffusion layer that extends on top of the gate dielectric layer, on inner sidewalls of the spacers, and on a portion of a front surface of embedding layers for the dummy gate structure. Providing the final gate electrode also includes providing a metal on top of the diffusion layer, applying an anneal step, and filling the area in between the inner sidewalls of the set of spacers with a final gate metal filling layer. The present disclosure also relates to an associated transistor.

Abstract: A method and system are described for performing extreme ultraviolet photolithographic processing. The method comprises obtaining a substrate comprising a hard mask and a patterned layer of extreme ultraviolet (EUV) photoresist formed above the hard mask, encapsulating the patterned layer of EUV photoresist by forming an encapsulating layer being one of a silicon-oxide, silicon-nitride, silicon-oxynitride, germanium-oxide, germanium-nitride, germanium-oxynitride, silicongermanium-oxide, silicongermanium-nitride, silicongermanium-oxynitride layer on the photoresist and dry etching of the substrate for patterning the hard mask. The encapsulation layer thereby is formed at a temperature below the weakening temperature Tg of the EUV photoresist by using a first precursor being one of the group of silicon-tetrahalogenide, silicon tetrahydride, germanium-tetrahalogenide, germanium tetrahydride, silicongermanium-tetrahalogenide or silicongermanium tetrahydride precursor and an oxygen precursor.

Abstract: A microprocessor configured to receive and process digitized signals derived from an analogue ECG signal is provided. An example microprocessor comprises a beat detection unit configured to receive the in-phase and quadrature phase band power signals, calculate a band power value and an adaptive threshold value, and compare said band power value with said adaptive threshold value to detect a QRS complex of the ECG signal indicative of a detected valid beat; and an R peak detection unit configured to receive the digital ECG signal and information about the detected valid beat, select a portion of the received ECG signal as a first time window around the detected valid beat; determine the location of a first R peak position; and perform a time domain search in a second time window around said first R peak position in order to refine the location of an R peak position.

Abstract: The present disclosure is related to a method for sharpening the tip of a microprobe, in particular a neural probe or an array of neuroprobes having a common base portion. The probes have a constant thickness and a chisel-shaped tip portion. The probes are attached to the slanted side of a wedge-shaped carrier, with the probe tips placed in close proximity to the edge of the carrier, for example extending over said edge. The base of the carrier is then subjected to a grinding step, possibly followed by a polishing step, so that the probe tips of the probes are ground to form a sharp pointed tip shape.

Abstract: The disclosed technology generally relates to sensors comprising a two-dimensional electron gas (2DEG), and more particularly to an AlGaN/GaN 2DEG-based sensor for sensing signals associated with electrocardiograms, and methods of using the same. In one aspect, a sensor comprises a substrate and a GaN/AlGaN hetero-junction structure formed on the substrate and configured to form a two-dimensional electron gas (2DEG) channel within the GaN/AlGaN hetero-junction structure. The sensor additionally comprises Ohmic contacts connected to electrical metallizations and to the 2DEG channel, wherein the GaN/AlGaN hetero-junction structure has a recess formed between the Ohmic contacts. The sensor further comprises a dielectric layer formed on a top surface of the sensor.

Abstract: An optical fluorescence-based sensor comprising at least one sensing element is disclosed. In one aspect, the at least one sensing element comprises a waveguide comprising a waveguide core, a light source optically coupled to an input part of the waveguide core, and a photodetector optically coupled to an output part of the waveguide core, the waveguide core being made of a material comprising a mixture of an optical material and a fluorescent dye.

Abstract: Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.

Abstract: A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel.

Abstract: A PV module is described with an array of PV cells whereby the module is reconfigurable, allowing different configurations to be applied after installation and during operation, i.e. at run-time. The run time configuration of the module has controllable devices. The main controllable devices are any of (individually or in combination): a) switches which determine the parallel/series connections of the cells as well as hybrid cases also. b) switches between the cells and local dc/dc converters and/or among the DC/DC converters; c) actively controlled bypass diodes placed in order to allow excess current to flow in the occurrence of a mismatch.