Patents Assigned to IMEC
-
Patent number: 8987749Abstract: The disclosed technology relates to a light-emitting diode (LED) and a method of fabricating the same. In one aspect, the LED includes a GaN p-n junction formed at a junction between a p-type GaN layer and an n-type GaN layer. The LED further includes a first metal electrode layer provided on the p-type GaN layer, where the first metal electrode layer is configured to reflect light emitted by the p-n junction towards a light emitting side of the LED. The LED additionally includes an attachment layer interposed between and configured to electrically connect the p-type GaN layer and the metal electrode layer, wherein the attachment layer comprises a transition metal oxide and is configured to transmit light emitted by the p-n junction and to transmit light reflected by the metal electrode layer.Type: GrantFiled: June 14, 2013Date of Patent: March 24, 2015Assignee: IMECInventors: Barry Rand, Celso Cavaco
-
Publication number: 20150073720Abstract: An example device includes: a data input module configured to receive information about a living being's physiological signals, coordinates, and motion intensity; an activity recognition module configured to calculate, from information received about the living being's motion intensity, a living being's activity; a location recognition module, configured to calculate, from information received about the living being's coordinates, a living being's location; a memory storage configured to store information about the living being's physiological signals and activity in association with the location; a normalization parameters estimator module configured to use a mathematical model to calculate a plurality of normalization parameters for a plurality of detected activities and locations; and a model selector module configured to determine, based on the plurality of normalization parameters and the living being's location, a set of location-specific normalization parameters used to further calculate normalized phyType: ApplicationFiled: August 28, 2014Publication date: March 12, 2015Applicant: STICHTING IMEC NEDERLANDInventor: Marco Altini
-
Patent number: 8974617Abstract: A method is provided for transferring a graphene sheet to metal contact bumps of a substrate that is to be used in a semiconductor device package, i.e. a stack of substrates connected by said contact bumps, e.g., copper contact bumps for which graphene forms a protective layer. An imprinter device can be used comprising an imprinter substrate, said substrate being provided with cavities, whereof each cavity is provided with a rim portion. The imprinter substrate is aligned with the substrate comprising the bumps and lowered onto said substrate so that each bump becomes enclosed by a cavity, until the rim portion of the cavities cuts through the graphene sheet, leaving graphene layer portions on top of each of bumps when the imprinter is removed. The graphene sheet is preferably attached to the substrate by imprinting it into a passivation layer surrounding the bumps.Type: GrantFiled: November 25, 2013Date of Patent: March 10, 2015Assignees: IMEC, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsiang Hu, Chung-Shi Liu
-
Patent number: 8975791Abstract: A patterned electret structure (21) on a substrate (10) comprises a dielectric structure comprising at least one non-patterned dielectric layer (22), and a charge pattern (14) in the dielectric structure and/or at a surface of a dielectric layer that is part of the dielectric structure and/or at an interface between dielectric layers that are part of the dielectric structure. By the presence of the non-patterned dielectric layer (22), the influence of the presence of a conductive substrate (10) on the charges (14) of the electret structure (21) is alleviated, hence increasing the charge stability over time. Moreover, in embodiments of the present invention, the charge stability is substantially independent of the width (W1, W2, W3) of the charge pattern. A method for manufacturing such patterned electret structure (21) is also provided.Type: GrantFiled: September 11, 2009Date of Patent: March 10, 2015Assignee: IMECInventor: Vladimir Leonov
-
Patent number: 8974870Abstract: Methods for fabricating porous low-k materials are provided, such as plasma enhanced chemically vapor deposited (PE-CVD) and chemically vapor deposited (CVD) low-k films used as dielectric materials in between interconnect structures in semiconductor devices. More specifically, a new method is provided which results in a low-k material with significant improved chemical stability and improved elastic modulus, for a porosity obtained.Type: GrantFiled: September 6, 2011Date of Patent: March 10, 2015Assignee: IMECInventors: Mikhail Baklanov, Quoc Toan Le, Laurent Souriau, Patrick Verdonck
-
Publication number: 20150064889Abstract: The present disclosure is related to a method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas. The method includes depositing an etch stop layer on the fins, depositing a BARC layer on the etch stop layer, depositing a resist layer on the BARC layer, removing a portion of the resist layer by lithography steps to thereby expose an area of the BARC layer, removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask, implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask, and removing the remainder of the resist and BARC layers.Type: ApplicationFiled: August 27, 2014Publication date: March 5, 2015Applicant: IMEC VZWInventors: Vasile Paraschiv, Gustaf Winroth, Efrain Altamirano Sanchez, Sabrina Locorotondo, Raja Athimulam
-
Patent number: 8969216Abstract: A method for single side texturing of a crystalline semiconductor substrate (10) comprises: providing a substrate (10), for example a semiconductor substrate, comprising a first surface (12) and a second surface (14) opposite to one another with respect to the substrate (10); providing a masking layer (21) with a random pattern on the first surface (12) of the substrate (10); and etching the substrate (10) in a polishing solution, thereby texturing the first surface (12) of the substrate (10) and polishing the second surface (14) in a single wet etching step.Type: GrantFiled: February 11, 2011Date of Patent: March 3, 2015Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Victor Prajapati, Joachim John
-
Patent number: 8971831Abstract: The present disclosure relates to a front-end system for a radio device, the front-end system comprising a low-noise amplifier (LNA), arranged for receiving a radio frequency input signal (RFIN) and arranged for outputting an amplified radio frequency signal (RFOUT), wherein the low-noise amplifier comprises a first differential amplifier, and a mixer (MIX), arranged for down-converting the amplified radio signal (RFOUT) provided by the low-noise amplifier (LNA) to a baseband signal (BB), by multiplying the amplified radio signal (RFOUT) with a local oscillator (LO) frequency tone, said low-noise amplifier (LNA) and said mixer (MIX) being inductively coupled.Type: GrantFiled: February 15, 2013Date of Patent: March 3, 2015Assignee: IMECInventors: Vojkan Vidojkovic, Kristof Vaesen, Piet Wambacq
-
Patent number: 8968864Abstract: A method for at least partially sealing a porous material is provided, comprising forming a sealing layer onto the porous material by applying a sealing compound comprising oligomers wherein the oligomers are formed by ageing a precursor solution comprising cyclic carbon bridged organosilica and/or bridged organosilanes. The method is especially designed for low k dielectric porous materials to be incorporated into semiconductor devices.Type: GrantFiled: September 18, 2012Date of Patent: March 3, 2015Assignees: IMEC, Universiteit GentInventors: Frederik Goethals, Pascal Van Der Voort, Isabel Van Driessche, Mikhail Baklanov
-
Patent number: 8962369Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.Type: GrantFiled: July 10, 2013Date of Patent: February 24, 2015Assignee: IMECInventors: Roger Loo, Frederik Leys, Matty Caymax
-
Patent number: 8963754Abstract: A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.Type: GrantFiled: September 10, 2013Date of Patent: February 24, 2015Assignees: IMEC, Stichting IMEC Nederland, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Alonso Morgado, Serena Porrazzo, Francesco Cannillo
-
Patent number: 8963225Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.Type: GrantFiled: September 12, 2013Date of Patent: February 24, 2015Assignees: IMEC, GLOBALFOUNDRIES Inc.Inventors: Benjamin Vincent, Geert Hellings, David Paul Brunco
-
Patent number: 8962304Abstract: The present disclosure is related to an interface device for providing access to a network to be monitored. The interface device includes a plurality of elements, the elements being sensors and/or actuators. A selection circuit is provided for selecting a subset of elements among the plurality of elements, each element of the subset being arranged for outputting and/or receiving a signal. A local memory is provided for storing the subset.Type: GrantFiled: February 28, 2008Date of Patent: February 24, 2015Assignee: IMECInventors: Roeland Huys, Wolfgang Eberle, Carmen Bartic
-
Patent number: 8961803Abstract: A method is provided for treating a surface of a porous material in an environment, the method comprising the steps of contacting a porous material with an organic gas in an environment having a pressure P1 and a temperature T1, wherein the organic gas is such that at the pressure P1 and at the temperature T1 it remains a gas when outside of the porous material but condenses as an organic liquid when in contact with the porous material, thereby filling pores of the porous material with the organic liquid, cooling down the filled porous material to a temperature T2 such that the organic liquid freezes within the pores, thereby sealing the pores with an organic solid, thereby providing a protected porous material, and performing a treatment on the surface.Type: GrantFiled: July 9, 2014Date of Patent: February 24, 2015Assignee: Imec VZWInventor: Mikhaïl Baklanov
-
Patent number: 8956453Abstract: The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a H2 flux or hydrogen originating from dissociation of GeH4 and/or to a non-reactive gas source such as N2, He, Ne, Ar, Kr, Xe, Rn or mixtures thereof, and crystallizing the amorphous germanium layer by annealing the base substrate so as to provide a crystalline germanium layer.Type: GrantFiled: July 18, 2008Date of Patent: February 17, 2015Assignees: IMEC, Vrije Universiteit BrusselInventors: Ruben Lieten, Stefan Degroote
-
Patent number: 8957794Abstract: An ADC includes sampling means for sampling an input voltage signal, comparator(s) for receiving the sampled signal, and a DAC including circuitry for generating a search signal approximating the input signal and a calibration signal. The search signal and the calibration signal are to be applied to a comparator. The ADC also includes a search logic block for receiving a comparator output signal, for providing input to the DAC for generating the search signal, and for producing a digital output signal. Further, the ADC includes a calibration logic block for producing a control signal to control the circuitry of the DAC and including processing means for observing the output signal, for comparing the output signal with a desired output, and for compensating analog non-idealities of the ADC. The DAC circuitry is adapted for generating the calibration signal in accordance with the control signal and with the sampled input signal.Type: GrantFiled: February 14, 2013Date of Patent: February 17, 2015Assignees: IMEC, Renesas Electronics CorporationInventors: Bob Verbruggen, Masao Iriguchi, Jan Craninckx
-
Patent number: 8958238Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.Type: GrantFiled: August 30, 2013Date of Patent: February 17, 2015Assignees: Stichting IMEC Nederland, Kathoieke Universiteit LeuvenInventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
-
Patent number: 8955381Abstract: A micromachined gyroscope is disclosed comprising a substrate, three masses m1, m2, and m3, configured to oscillate along a first direction x or y, whereby the first mass m1 is mechanically coupled to the substrate, the second mass m2 is mechanically coupled to the first mass m1 and to substrate, and the third mass m3 is mechanically coupled to the second mass m2, whereby the weight and the spring constants k1, k2, k3 of the respective masses m1, m2, and m3 and mechanical couplings k12, k23 are selected, such that, during operation mass m2 oscillates at a frequency substantially above the resonance frequencies of mass m1 and mass m3. The resonance frequency of mass m2 may be at least 2 times, or even 2.5 times, higher than the resonance frequency of mass m1 or m3.Type: GrantFiled: September 13, 2012Date of Patent: February 17, 2015Assignee: IMECInventor: Mehmet Akif Erismis
-
Publication number: 20150028428Abstract: A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.Type: ApplicationFiled: July 25, 2014Publication date: January 29, 2015Applicants: KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&D, IMEC VZWInventors: Han Chung Lin, Laura Nyns, Tsvetan Ivanov, Dennis Van Dorp
-
Publication number: 20150021202Abstract: The disclosure relates to a device for electrochemical gas sensing, comprising a plurality of different electrodes and a freestanding electrolyte film covering said electrodes, wherein at least two of those electrodes present a different distance from its top surface to the electrolyte film surface. The disclosure also relates to an electronic system and a method for electrochemical gas sensing.Type: ApplicationFiled: July 17, 2014Publication date: January 22, 2015Applicant: Stichting IMEC NederlandInventors: Jozef Franciscus Maria Oudenhoven, Greja Johanna Adriana Maria Verheyden, Marcel Arie Günther Zevenbergen