Patents Assigned to IMEC
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Publication number: 20140176082Abstract: An antenna arrangement for transmitting energy is described. The antenna arrangement includes a planar array of two or more rectangular loop antennas, adapted to transmit energy at low frequencies via non-radiative resonant coupling and at high frequencies via radiative coupling. The low frequencies correspond to a wavelength with half of the wavelength being larger than the longest rectangular loop antenna dimension and the high frequencies correspond to a wavelength with half of the wavelength being approximately equal the longest rectangular loop antenna dimension. The antenna arrangement also includes a feeding network connected to the planar array, which includes a phase shifting means for providing a phase difference between signals at the high frequencies to be transmitted by different rectangular loop antennas of the planar array, whereby the amount of phase difference is related to the distance of the rectangular loop antennas to a focal point in the near-field of the planar array.Type: ApplicationFiled: December 11, 2013Publication date: June 26, 2014Applicant: STICHTING IMEC NEDERLANDInventor: Hubregt Jannis Visser
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Publication number: 20140176199Abstract: Various active diode circuits are described. In one example, there is provided an active diode circuit having an active diode and a control circuit. The active diode includes an anode terminal, a cathode terminal and a control terminal. The control circuit is configured to generate a control current of the active diode on the control terminal proportional to the diode current of the active diode. The control circuit is also configured to control the diode voltage of the active diode below a predetermined threshold.Type: ApplicationFiled: November 15, 2013Publication date: June 26, 2014Applicant: Stichting IMEC NederlandInventor: Christinus Antonetta Paulus van Liempd
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Publication number: 20140176957Abstract: A photonics integrated system is disclosed, comprising a substrate, an integrated interferometer integrated in the substrate and being configured for receiving radiation from a radiation source, and an integrated spectral filter integrated in the substrate and being configured for receiving radiation from the interferometer. The integrated interferometer has a period and the integrated spectral filter has a bandwidth such that the period of the integrated interferometer is smaller than the bandwidth of the integrated spectral filter. The integrated spectral filter has a periodic transfer characteristic with a period and the system has a bandwidth such that the period of the periodic transfer characteristic of the integrated spectral filter is larger than the bandwidth of the system.Type: ApplicationFiled: December 20, 2013Publication date: June 26, 2014Applicants: IMEC, UNIVERSITEIT GENTInventors: Peter BIENSTMAN, Tom CLAES
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Publication number: 20140176388Abstract: A tunable impedance network and a method for tuning the tunable impedance network are disclosed. In one aspect, the tunable impedance network comprises a plurality of transformers connected in series. Each transformer has a primary winding and a secondary winding. The transformers have a voltage transformation ratio of N:1 with N>1. An impedance structure, acting as a resonant circuit together with the inductance of the secondary winding, is connected at the secondary winding of each transformer. A control circuit or processor is configured to tune the imaginary part of at least one of the impedance structures so as to change its resonance frequency to mimic a reference impedance. The control circuit is further configured to tune the real part of at least one of the impedance structures so as to change its Q-factor to mimic the reference impedance.Type: ApplicationFiled: December 17, 2013Publication date: June 26, 2014Applicant: IMECInventors: Barend Van Liempd, JONATHAN BORREMANS
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Publication number: 20140179054Abstract: The disclosed technology generally relates to forming patterns of doped semiconductor regions, and more particularly to methods of forming such patterns in fabricating photovoltaic devices. In one aspect, a method of forming a pattern of different doped regions at the same side of a semiconductor substrate comprises providing a patterned doped layer on a surface of the semiconductor substrate at predetermined locations where at least one first doped region is to be formed. The method additionally includes selectively growing at least one second doped region epitaxially at the same side of the semiconductor substrate using the patterned doped layer as an epitaxial growth mask. Furthermore, selectively growing comprises driving dopants from the patterned doped layer into the semiconductor substrate to form the first doped region at the predetermined locations.Type: ApplicationFiled: February 4, 2014Publication date: June 26, 2014Applicant: IMECInventors: Maria Recaman Payo, Niels Posthuma
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Publication number: 20140175676Abstract: A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.Type: ApplicationFiled: December 11, 2013Publication date: June 26, 2014Applicant: IMECInventors: Philippe Soussan, Melina Lofrano
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Publication number: 20140175891Abstract: A current generator is disclosed. An example current generator includes a plurality of current cells connected in parallel, each current cell being connected to a switch. The current generator further includes a first summer configured to sum the output of each current cell of a first subset of the plurality of current cells and a second summer configured to sum the output of each current cell of a second subset of the plurality of current cells. The current generator also includes a combiner configured to combine the outputs of the first and second summers. Further, each switch is switchable according to a sequence to generate a summed output of the current cells at a plurality of quantization levels to generate positive and/or negative alternations of a pseudo-sinusoidal, alternating current.Type: ApplicationFiled: December 16, 2013Publication date: June 26, 2014Applicant: IMECInventors: Sunyoung Kim, Refet Firat Yazicioglu
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Patent number: 8758688Abstract: The present invention is related to the localized/patterned deposition and/or desorption of (bio)molecules using microelectronic structures. Often pre-existing structures needed for proper functioning of the device (e.g. sensors, . . . ) can be used as individually addressable control structures to achieve localized deposition through thermal and/or electrochemical spotting, thereby reducing the need for and simplifying additional processing steps to achieve localized/patterned deposition. If these multi-purpose structures are not available, additional control structures can be implemented, using microelectronic VLSI production technology.Type: GrantFiled: December 22, 2004Date of Patent: June 24, 2014Assignees: IMEC, Katholieke Universiteit LeuvenInventors: Koen De Keersmaecker, Gustaaf Borghs, Piet Herdewijn
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Publication number: 20140170837Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.Type: ApplicationFiled: December 13, 2013Publication date: June 19, 2014Applicant: IMECInventors: Benjamin Vincent, Geert Eneman
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Publication number: 20140169237Abstract: A circuit for reducing counter-intermodulation in a modulated signal caused by an oscillator frequency and harmonics of a baseband signal is disclosed. The circuit comprises a first and a second baseband section arranged for generating a first and a second version of a baseband signal, the second version being phase shifted with respect to the first version. The circuit further comprises three signal paths comprising mixers for multiplication of the first and second version of the baseband signal with a local oscillator signal, so that three upconverted signals with rotated phase with respect to each other are obtained, and arranged for applying a scaling with a scaling factor corresponding to the rotated phases. The circuit further comprises a combination unit arranged for combining the three upconverted signals.Type: ApplicationFiled: December 17, 2013Publication date: June 19, 2014Applicants: RENESAS Electronics Corporation, IMECInventors: Yoshikazu Furuta, Mark Maria Albert Ingels
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Publication number: 20140169724Abstract: Thermally stabilised resonant electro-optic modulator (1), wherein the temperature control unit (8) is provided for separately determining the first and the second intensities measured by the light sensor (6) at the first voltages and the second voltages respectively in function of time.Type: ApplicationFiled: December 12, 2013Publication date: June 19, 2014Applicant: IMECInventor: Mark Maria Albert Ingels
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Patent number: 8755868Abstract: A method and apparatus is disclosed for adaptively sampling an analogue signal to increase the sampling rate in the presence of high frequency content within the signal, for example, QRS complex of an ECG signal. In one aspect, a change in a derivative of the analogue signal is used to control a voltage-controlled oscillator to provide a clock signal for an analogue-to-digital converter. The change in the derivative is compared to an automatically controlled threshold value. The clock signal controls the sampling rate of the analogue-to-digital converter so that the sampling rate is increased from one level, where only P and T waves are present to another higher level when the QRS complex has been detected.Type: GrantFiled: September 14, 2010Date of Patent: June 17, 2014Assignee: IMECInventor: Refet Firat Yazicioglu
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Publication number: 20140159118Abstract: Disclosed are semiconductor devices and methods for manufacturing them. An example device may include a III-nitride stack having a front side surface and a back side surface. The III-nitride stack may be formed of at least a first layer and a second layer, between which a heterojunction may be formed, such that a two-dimensional electron gas layer is formed in the second layer. A source electrode, a drain electrode, and a gate electrode positioned between the source and drain electrodes may be formed on the front side surface, and an insulation layer may be formed over the electrodes on the front side surface. A carrier substrate may be attached to the insulation layer. An electrically conductive back plate may be formed on the back side surface. The back plate may directly face the source electrode and the gate electrode, but not the drain electrode.Type: ApplicationFiled: December 10, 2013Publication date: June 12, 2014Applicant: IMECInventors: Sylvia Lenci, Stefaan Decoutere
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Publication number: 20140160835Abstract: A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material.Type: ApplicationFiled: December 4, 2013Publication date: June 12, 2014Applicant: IMECInventors: Bart Soree, Marc Heyns, Geoffrey Pourtois
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Publication number: 20140161384Abstract: One aspect of the invention relates to a photonic device having a wavelength-dependent transmission or filter characteristic, comprising: a Splitter Polarization Rotator receiving polarized light and providing a first resp. second wave; a first resp. second waveguide arm connected to the SPR for propagating a first resp. second polarization mode (TM, TE) of the first resp. second wave, the second polarization mode being different from the first polarization mode; and a Polarization Rotator and Combiner for combining the propagated first resp. second waves; wherein the dimensions of the first and second arm are selected to cancel the influence of an external effect on the wavelength-dependent characteristic. Another aspect of the invention relates to a method for reducing the sensitivity of said integrated photonic device, comprising splitting a polarized light beam, propagating light waves of different polarity through two waveguide arms of specific dimensions, and recombining them.Type: ApplicationFiled: December 5, 2013Publication date: June 12, 2014Applicants: UNIVERSITEIT GENT, IMECInventors: Sarvagya Dwivedi, Wim Bogaerts
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Publication number: 20140151766Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.Type: ApplicationFiled: November 21, 2013Publication date: June 5, 2014Applicant: IMECInventors: Geert Eneman, Benjamin Vincent, Voon Yew Thean
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Publication number: 20140151848Abstract: The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP is formed between a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers.Type: ApplicationFiled: November 27, 2013Publication date: June 5, 2014Applicant: IMECInventors: Mikael Detalle, Eric Beyne
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Patent number: 8741684Abstract: Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer.Type: GrantFiled: May 8, 2012Date of Patent: June 3, 2014Assignees: IMEC, Universiteit GentInventors: Wim Bogaerts, Joris Van Campenhout, Peter Verheyen, Philippe Absil
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Patent number: 8742590Abstract: A method is provided for forming at least one TSV interconnect structure surrounded by at least one isolating trench-like structure having at least one airgap. The method comprises at least the steps of providing a substrate having a first main surface and producing simultaneous at least one a TSV hole and a trench-like structure surrounding the TSV hole and separated by remaining substrate material. The method also comprises thereafter depositing a dielectric liner in order to smoothen the sidewalls of the etched TSV hole and to pinch-off the opening of the trench-like structure at the first main surface of the substrate in order to create at least one airgap in said trench-like structure and depositing a conductive material in said TSV hole in order to create a TSV interconnect. A corresponding substrate is also provided.Type: GrantFiled: December 2, 2011Date of Patent: June 3, 2014Assignee: IMECInventor: Eric Beyne
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Patent number: 8743849Abstract: A method for performing, for a plurality of applications, data communication on a wireless medium accessible for a plurality of nodes used by the applications is disclosed. Each application is assigned to one of a plurality of application classes. In one aspect, the method includes sending, at one of the plurality of nodes, a resource request for an application via a control channel dedicated to the application class which the application is assigned to, wherein the resource request is sent employing an access method available for the application class. The method also includes taking a decision on allocating resource on the wireless medium for the application. The method also includes performing data communication for the application via a conflict-free data channel, the data channel being separated in time from the dedicated control channel.Type: GrantFiled: January 28, 2010Date of Patent: June 3, 2014Assignee: Stichting IMEC NederlandInventor: Yan Zhang