Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

Abstract: The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract: A method for manufacturing a dual work function semiconductor device and the device made thereof are disclosed. In one aspect, a method includes providing a gate dielectric layer over a semiconductor substrate. The method further includes forming a metal layer over the gate dielectric layer. The method further includes forming a layer of gate filling material over the metal layer. The method further includes patterning the gate dielectric layer, the metal layer and the gate filling layer to form a first and a second gate stack. The method further includes removing the gate filling material only from the second gate stack thereby exposing the underlying metal layer. The method further includes converting the exposed metal layer into an metal oxide layer. The method further includes reforming the second gate stack with another gate filling material.

Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.

Abstract: A system for the acquisition of biopotential signals, comprising at least a first electrode configured for detecting a biopotential signal within a signal bandwidth of interest and being connected to an impedance detection module that provides a first electrode voltage. The impedance detection module comprises a current generation circuit connected in parallel to an amplifier. The current generation circuit comprises an AC current generator configured to generate a first current signal through the first electrode. The first current signal has a frequency outside of the signal bandwidth of interest. The current generation circuit also comprising a capacitor connected between the input of the amplifier and the AC current generator so as to isolate the AC current generator from the amplifier input at the signal bandwidth of interest.

Abstract: The embodiments disclose a silicon substrate with a group III-V material and a method for fabricating a group III-V material on a silicon substrate. The method involves providing a silicon substrate. A first layer formed atop the silicon substrate, is subsequently patterned to expose the underlying silicon substrate. A group III-V material layer is formed over the patterned first layer and also on the exposed silicon substrate. The group III-V material layer is subjected to chemical mechanical polishing (CMP) to expose the first layer resulting in the formation of a plurality of areas suitable for growing a device layer on the silicon substrate.

Abstract: The present disclosure relates to a circuit for providing a signal gain, comprising: a first stage comprising a first set of variable gain transconductors arranged for receiving an input signal and for performing phase-shifting of the input signal, thereby producing an intermediate signal, and a second stage, comprising a second set of transconductors and a plurality of capacitors arranged for receiving the intermediate signal and for providing an output signal to a combiner, wherein the first stage and second stage together form a filter, and wherein the first set of variable gain transconductors and at least one of the transconductors of the second set define the signal gain of the circuit.

Abstract: A method for module-level processing of photovoltaic cells is provided. The method includes: bonding at least one crystalline silicon photovoltaic substrate to a carrier by means of an adhesive layer, thereby leaving part of the adhesive layer uncovered; after bonding, exposing the uncovered part of the adhesive layer and the at least one crystalline silicon photovoltaic substrate to a plasma; and removing a surface portion of the at least one crystalline photovoltaic substrate. The method may further include performing an annealing step of the adhesive before bonding the at least one photovoltaic substrate to the carrier, and performing an outgassing step of the adhesive after bonding the at least one photovoltaic substrate to the carrier. The method may further include module-level rear side processing of the at least one crystalline silicon photovoltaic substrate to make a photovoltaic module.

Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures.

Abstract: A micro-fluidic device for mapping a DNA or RNA strand labeled at a plurality of specific sites with labels suitable for generating a detection signal when interacting with a detector element, the device comprising: a micro-fluidic channel; and a plurality of detector elements for detecting the labels by acquiring the detection signals, the detector elements being positioned longitudinally along the micro-fluidic channel, each detector element having a width, successive detector elements being separated by an inter-detector gap having a width, wherein the widths of at least two of the detector elements are different and/or wherein the widths at least two of the inter-detector gaps are different.

Abstract: The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.

Abstract: Various active diode circuits are described. In one example, there is provided an active diode circuit having an active diode and a control circuit. The active diode includes an anode terminal, a cathode terminal and a control terminal. The control circuit is configured to generate a control current of the active diode on the control terminal proportional to the diode current of the active diode. The control circuit is also configured to control the diode voltage of the active diode below a predetermined threshold.

Abstract: A method involving ion milling is demonstrated to fabricate open-nanoshell suspensions and open-nanoshell monolayer structures. Ion milling technology allows the open-nanoshell geometry and upward orientation on substrates to be controlled. Substrates can be fabricated covered with stable and dense open-nanoshell monolayer structures, showing nanoaperture and nanotip geometry with upward orientation, that can be used as substrates for SERS-based biomolecule detection.

Abstract: A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic.

Abstract: The present disclosure relates to a device for analyzing a fluid sample. In one aspect, the device includes a fluidic substrate that comprises a micro-fluidic component embedded in the fluidic substrate configured to propagate a fluid sample via capillary force through the device and a means for providing a fluid sample connected to the micro-fluidic component. The device also includes a lid attached to the fluidic substrate at least partly covering the fluidic substrate and at least partly closing the micro-fluidic component. The fluidic substrate may be a silicon fluidic substrate and the lid may be a CMOS chip. In another aspect, embodiments of the present disclosure relate to a method for fabricating such a device, and the method may include providing a fluidic substrate, providing a lid, and attaching, through a CMOS compatible bonding process, the fluidic substrate to the lid to close the fluidic substrate at least partly.

Abstract: The present disclosure relates to a method (100) for depositing a layer on a III-V semiconductor substrate, in which this method comprises providing (102) a passivated III-V semiconductor substrate comprising a III-V semiconductor surface which has a surface passivation layer provided thereon for preventing oxidation of said III-V semiconductor surface. The surface passivation layer comprises a self-assembled monolayer material obtainable by the reaction on the surface of an organic compound of formula R-A, wherein A is selected from SH, SeH, TeH and SiX3. X is selected from H, Cl, O—CH3, O—C2H5, and O—C3H2, and R is a hydrocarbyl, fluorocarbyl or hydrofluorocarbyl comprising from 5 to 20 carbon atoms. The method further comprises thermally annealing (107) the III-V semiconductor substrate in a non-oxidizing environment such as to decompose the self-assembled monolayer material, and depositing (108) a layer on the III-V semiconductor surface in the non-oxidizing environment.

Abstract: The present disclosure relates to methods for determining recombination characteristics at metallized semiconductor surfaces and of metallized semiconductor junctions, based on photo-conductance decay measurements. Dedicated test structures are used comprising a plurality of metal features in contact with a semiconductor surface at predetermined locations, the metal features being provided in a plurality of zones, each of the plurality of zones having a different metal coverage. The method comprises performing a photo-conductance decay measurement in each of the plurality of zones, thereby determining effective lifetimes for different injection levels as a function of metal coverage; and extracting the recombination characteristics from the determined effective lifetimes.