Abstract: This present application relates to a system for delivering megasonic energy to a liquid, involving one or more megasonic transducers, each transducer having a single operating frequency within an ultrasound bandwidth and comprising two or more groups of piezoelectric elements arranged in one or more rows, and a megasonic generator means for driving the one or more transducers at frequencies within the bandwidth, the generator means being adapted for changing the voltage applied to each group of piezoelectric elements so as to achieve substantially the same maximum acoustic pressure for each group of piezoelectric elements. The generator means and transducers being constructed and arranged so as to produce ultrasound within the liquid. Such a system may be part of an apparatus for cleaning a surface of an article such as a semiconductor wafer or a medical implant.

Abstract: A method for defining regions with different surface liquid tension properties on a substrate is disclosed. The method includes: providing a substrate with a main surface having a first surface liquid tension property that is at least partially covered with a seed layer; forming at least one micro-bump on the seed layer leaving part of the seed layer exposed; patterning the exposed seed layer to expose part of the main surface; forming at least one closed-loop structure that encloses a region of the main surface and the at least one micro-bump; and chemically treating the main surface of the substrate to provide on a surface of at least one closed-loop structure and the at least one micro-bump a second surface liquid tension property. The second surface liquid tension property is substantially different from the first surface liquid tension property of the main surface and is liquid phobic.

Abstract: A method for fabricating an out-of-plane variable overlap MEMS capacitor comprises: providing a substrate (40) comprising a first layer (41), a second layer (42), and a third layer (43) stacked on top of one another; and etching a plurality of first trenches (70) through the third layer (43), through the second layer (42), and into the first layer (41) using a single etching mask. Etching the plurality of first trenches (70) defines a plurality of first fingers (51) in the third layer (43) and a plurality of second fingers (52) in the first layer (41). By using a single mask, the process is self-aligned. The method further comprises removing the second layer (42) in a first region where the plurality of first trenches (70) are provided, thereby forming a spacing or gap between the plurality of first fingers (51) and the plurality of second fingers (52).

Abstract: An amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an input configured to receive an input signal. The amplifier circuit further includes an amplifier connected to the input that is configured to receive the input signal and generate a modulated input signal based on the input signal and one of a first amplification level and a second amplification level. The amplifier comprises a first transistor configured to receive the input signal and a second transistor connected in cascode with the first transistor. The amplifier circuit further includes a switching component configured to switch the amplifier between the first amplification level and the second amplification level. The amplifier circuit still further includes an output connected to the amplifier and configured to output the modulated input signal.

Abstract: The present invention is related to a front-end circuit for an optical communication system including a laser module arranged for transmitting bursts of data signals over an optical network and a driving circuit for providing the bursts of data signals to the laser module. The front-end circuit further includes receiver means in connection with said laser module and arranged for receiving from the optical network optical echo signals. The laser module includes a laser diode arranged for transmitting the bursts of data signals. The driving circuit is arranged for setting a disabling signal for stopping the laser diode from transmitting bursts of the data signals. Fiber-related information can be extracted from the echo signals, such as distance-resolved optical fiber reflections and fiber attenuation.

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract: A method of fabricating a field-effect transistor is disclosed. In one aspect, the method includes forming a channel layer comprising germanium over a substrate. The method additionally includes forming a gate structure on the channel layer, where the gate structure comprises a gate layer comprising silicon, and the gate layer has sidewalls above a surface of the channel layer. The method additionally includes forming sidewall spacers comprising silicon dioxide on the sidewalls by subjecting the gate structure to a solution adapted for forming a chemical silicon oxide on materials comprising silicon. The method further includes forming elevated source/drain structures on the channel layer adjacent to the gate structure by selectively epitaxially growing a source/drain material on the channel layer.

Abstract: A compliable unit in an compliable network comprises a first layer including at least one device component at a first region of the first layer, and a second layer including at least one compliable element at a first region of the second layer to transfer the at least one device component to a desired location. The first layer and the second layer are arranged in a stack.

Abstract: Ultra-low capacitance interconnect structures, preferably Through Silicon Via (TSV) interconnects and methods for fabricating said interconnects are disclosed. The fabrication method comprises the steps of providing a substrate having a first main surface, producing at least one hollow trench-like structure therein from the first main surface, said trench-like structure surrounding an inner pillar structure of substrate material, depositing a dielectric liner which pinches off said hollow trench-like structure at the first main surface such that an airgap is created in the center of hollow trench-like structure and further creating a TSV hole and filling it at least partly with conductive material.

Abstract: Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an H2O oxidant to deposit on the first metal layer a protective layer comprising TiO2. The method further includes using atomic layer deposition with an O3 oxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO2, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.

Abstract: A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters.

Abstract: The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including a) providing a substrate, and b) depositing a layer of material on said substrate via ALD at a temperature of from 250 to 500° C., said depositing step comprising: at least one HfX4 pulse, and at least one trimethyl-aluminum (TMA) pulse, wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.

Abstract: A method for reducing defects in an active device area of a semiconductor device during fabrication is disclosed. In one aspect, the method comprises providing the active device area adjacent an isolation structure, wherein a substantially planar surface is formed over the isolation structure and the active device area, forming a patterned stress-inducing layer over the substantially planar surface, forming at least one screening layer between the patterned stress-inducing layer and the substantially planar surface, where the screening layer is configured to screen part of the stress field induced by the patterned stress-inducing layer, performing an anneal process after forming the patterned stress-inducing layer on the substantially planar surface, so as to induce a movement of the defects towards a contact interface between the active device area and the isolation structure, and removing the patterned stress-inducing layer from the substantially planar surface.

Abstract: A DND device is disclosed. In one aspect, the device includes a nano-mirror (21), and an actuating module configured to move the nano-mirror in an upward and/or downward position. The actuating module has a cantilever mounted to a fixed structure, and at least one first electrode for moving the cantilever in an upward and/or downward position. Such DND devices may be arranged in a 2D array.

Abstract: Photonic structures and methods of operating the photonic structures are disclosed. In one embodiment, the photonic structure includes a detector configured to detect radiation of a first wavelength range. The radiation of the first wavelength range is received from an external radiation guide, and the detector is substantially transparent to radiation of a second wavelength range that differs from the first wavelength range. The photonic structure further includes a coupling structure configured to free space couple out of the photonic structure radiation of the second wavelength range. The photonic structure further includes a guiding structure configured to optically guide the radiation of the second wavelength range through the detector.

Abstract: A method for estimating transceiver non-idealities is disclosed. In one aspect, the method comprises generating a preamble comprising multiple sets of known training sequences with a synchronization part preceding an estimation part. The training sequences in the estimation part comprises at least two sequences which are (i) complementary Golay sequence pairs and (ii) selected to satisfy a predetermined correlation relationship chosen for estimation of a first non-ideality characteristic. A first estimate of a non-ideality characteristic is determined on the basis of the known training sequences of the synchronization part of the received preamble. The estimation part of the received preamble is compensated by this estimate. Another non-ideality characteristic is determined by the compensated estimation part, exploiting the predetermined correlation relationship.

Abstract: Methods and sensors for detecting the presence and/or concentration of an analyte are disclosed. In one aspect, a sensing element for use in a sensor is disclosed. The sensing element comprises a resonant cavity device configured to emit optical radiation at an initial power level, a sensing layer exhibiting an initial refractive index, and a detector. The sensing layer is configured to absorb or adsorb an analyte and, in response to absorbing or adsorbing the analyte, exhibit a modified refractive index that differs from the initial refractive index. The resonant cavity device is further configured to, in response to the sensing layer absorbing or adsorbing the analyte, emit optical radiation at a modified power level based on the modified refractive index. The detector is configured to detect the modified power level.

Abstract: A method for determining an active dopant concentration profile of a semiconductor substrate based on optical measurements is disclosed. The active dopant concentration profile includes a concentration level and a junction depth. In one aspect, the method includes obtaining a photomodulated optical reflectance (PMOR) amplitude offset curve and a PMOR phase offset curve for the semiconductor substrate based on PMOR measurements, determining a decay length parameter based on a first derivative of the amplitude offset curve, determining a wavelength parameter based on a first derivative of the phase offset curve, and determining, from the decay length parameter and the wavelength parameter, the concentration level and the junction depth of the active dopant concentration profile.

Abstract: The invention relates to an assembly for detecting the presence of a target based on a detection of a resonance associated to surface polaritons, such as long-range surface exciton polaritons (LRSEP). The invention relates to an assembly to be used in connection with a bio-sensor. The assembly comprising a carrier substrate (1) and a sensor layer (2) positioned on the carrier substrate. The sensor layer is of a material having a complex permittivity with an imaginary part being greater than or similar to the real part.

Abstract: A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gate electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.