Abstract: A method of manufacturing a dual work function semiconductor device is disclosed. In one aspect, the method includes providing a substrate having first and second areas for forming first and second transistor types. The method additionally includes forming a dielectric layer on the substrate, which extends to cover at least parts of the first and second areas. The method additionally includes forming a first metal layer/stack on the dielectric layer in the first area, where the first metal layer/stack comprises a first work function-shifting element. The method additionally includes forming a second metal layer/stack on the first metal layer in the first area and on the dielectric layer in the second area, where the second metal layer/stack comprises a second work function-shifting element.

Abstract: The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material.

Abstract: The present invention relates to a coupler (100) for coupling radiation to one optical element. The coupler (100) comprises a splitter (110) for splitting a received radiation beam in at least two radiation sub-beams, at least two distinct sub-gratings (120a, 120b) adapted for directing radiation sub-beams such that all radiation is coupled out by the coupler into substantially one direction, and a means for guiding (130a, 130b) each of the radiation sub-beams between the splitter and a sub-grating (120a, 120b).

Abstract: An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region.

Abstract: Disclosed are methods for forming fins. In an example embodiment, a method includes providing a substrate that includes at least two elongated structures separated by an isolation region. Each elongated structure comprises a semiconductor alloy of a first semiconductor material and a second semiconductor material, and a relaxed portion of the elongated structure includes the semiconductor alloy in a relaxed and substantially defect-free condition. The method further includes subjecting the substrate to a condensation-oxidation, such that each elongated structure forms a fin and an oxide layer. The fin includes a fin base portion formed of the semiconductor alloy and a fin top portion of the first semiconductor material in a strained condition. The fin top portion is formed by condensation of the first semiconductor material. The oxide layer includes an oxide of the second semiconductor material. The method further includes removing at least some of the oxide layer.

Abstract: A method for porogen removal of porous SiOCH film is provided, as well as devices obtained thereof. The devices and associated methods are in the field of advanced semiconductor interconnect technology, and more in particular in the development of dielectric films with low-k value.

Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.

Abstract: The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines. The memory device further comprises a memory controller connected to and configured to apply voltages to the bit lines, the word lines, the source lines and the form lines. In addition, each of the memory cells comprises a cell selecting transistor and a resistive memory element serially connected to a drain-source path of the cell selecting transistor. Furthermore, each of the memory cells comprises a boosting capacitor configured to provide a boosting a voltage to an internal node formed at a connection point between the resistive memory element and the cell selecting transistor.

Abstract: A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 1017 atoms/cm3 to be obtained.

Abstract: A method and system for testing the functionality of a through-silicon-via in an integrated circuit is disclosed. In one aspect, the functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. The comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.

Abstract: Disclosed are methods for fabricating pyrolysed carbon nanostructures. An example method includes providing a substrate, depositing a polymeric material, subjecting the polymeric material to a plasma etching process to form polymeric nanostructures, and pyrolysing the polymeric nanostructures to form carbon nanostructures. The polymeric material comprises either compounds with different plasma etch rates or compounds that can mask a plasma etching process. The plasma etching process may be an oxygen plasma etching process.

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

Abstract: A photonics integrated circuit for processing radiation includes a first-dimensional grating coupler for coupling in radiation, a second two-dimensional grating coupler for coupling out radiation and a waveguide structure having two distinct waveguide arms for splitting radiation received from the first grating coupler and recombining radiation in the second grating coupler. A phase shifting means furthermore is provided for inducing an additional phase shift in at least one of the two distinct waveguide arms thereby inducing a relative phase shift of ? between the two distinct waveguide arms so as to provide a TE/TM polarization switch for radiation between the first grating coupler and the second grating coupler.

Abstract: A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quanitzer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.

Abstract: A memory device having complementary global and local bit-lines, the complementary local bit-lines being connectable to the complementary global bit-lines by means of a local write receiver which is configured for creating a full voltage swing on the complementary local bit lines from a reduced voltage swing on the complementary global bit lines. The local write receiver comprises a connection mechanism for connecting the local to the global bit-lines and a pair of cross-coupled inverters directly connected to the complementary local bit lines for converting the reduced voltage swing to the full voltage swing on the complementary local bit lines.

Abstract: A DC-DC converter and a method of controlling an inductor-based switching-mode DC-DC converter in a discontinuous conduction mode are disclosed. In one aspect the method includes providing a DC-DC converter having a first and second switching elements, and, in each conversion cycle, first, turning on a first switching element, while maintaining a second switching element in off state, thereby increasing the current through an inductor. The method also includes detecting when a voltage signal at one connection node of the inductor reaches a first threshold value for the first time after the start of the conversion cycle, and turning on the second switching element, while maintaining the first switching element in off state, thereby decreasing the inductor current.

Abstract: The disclosure is related to an SSRM method for measuring the local resistivity and carrier concentration of a conductive sample. The method includes contacting the conductive sample at one side with an AFM probe and at another side with a contact electrode, modulating, at a modulation frequency, the force applied to maintain physical contact between the AFM probe and the sample while preserving the physical contact between the AFM probe and the sample, thereby modulating at the modulation frequency the spreading resistance of the sample; measuring the current flowing through the sample between the AFM probe and the contact electrode; and deriving from the measured current the modulated spreading resistance. Deriving the modulated spreading resistance includes measuring the spreading current using a current-to-voltage amplifier, converting the voltage signal into a resistance signal, and filtering out from the resistance signal, the resistance amplitude at the modulation frequency.

Abstract: A method for manufacturing a transistor device is provided, the transistor device comprising a germanium based channel layer, the method comprising providing a gate structure on the germanium comprising channel layer provided on a substrate, the gate structure being provided between a germanium based source area and a germanium based drain area at opposite sides of the germanium comprising channel layer; providing a capping layer on the germanium based source and the germanium based drain area, the capping layer comprising Si and Ge; depositing a metal layer on the capping layer; performing a temperature step, thereby transforming at least part of the capping layer into a metal germano-silicide which is not soluble in a predetermined etchant adapted for dissolving the metal; selectively removing non-consumed metal from the substrate by means of the predetermined etchant; and providing a premetal dielectric layer.

Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.

Abstract: A method is disclosed for passivating and contacting a surface of a germanium substrate. A passivation layer of amorphous silicon material is formed on the germanium surface. A contact layer of metal, e.g., aluminum, is then formed on the passivation layer. The structure is heated so that the germanium surface makes contact with the contact layer. The aluminum contact layer can be configured for use as a mirroring surface for the back surface of the device. Thus, a passivated germanium surface is disclosed, as well as a solar cell comprising such a structure.