Abstract: A method for accessing an SRAM cell includes: determining whether an access is a read access or write access, applying a read word line pulse having a first width to a word line if the access is a read access, and applying a write word line pulse having a second width to the word line if the access is a write access, wherein the first and second widths are different. The method can further include: pre-charging a bit line pair of the SRAM cell for a first pre-charge period after de-asserting the read word line pulse, and pre-charging the bit line pair for a second pre-charge period after de-asserting the write word line pulse, wherein the first and second pre-charge periods are different. The cycle time of the SRAM cell is reduced by providing word line pulses having only the necessary widths and pre-charge operations having only the necessary periods.

Abstract: Complementary data line driver circuits conserve power by evaluating data on complementary data lines and providing conditional charge recycling in the event the new data to be provided to the complementary data lines differs from the old data residing thereon. These devices and circuits include first and second data lines within a complementary data line pair and a driver control circuit that is electrically coupled to the data line pair. The driver control circuit compares the old data on the data line pair against new data to be provided to the data line pair. Based on the comparison and determination that the old data is opposite the new data, the driver control circuit switches the old data to the new data in two steps. The first of the two steps includes transferring charge from the more positively biased one of the first and second data lines to the other data line in the data line pair, preferably for a duration sufficient to substantially equilibrate voltages on the first and second data lines.

Abstract: A FIFO memory device includes an embedded memory array having a write port and a read port and a quad-port cache memory device. The cache memory device has a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port and a second embedded memory port that is electrically coupled to the read port. A data input register, a retransmit register, a data output register and a multiplexer are provided within the cache memory device. The data input register is responsive to a write address and has a data input electrically coupled to the data input port and a data output electrically coupled to the first embedded memory port. The retransmit register is responsive to a retransmit address and has a data input electrically coupled to the data input port.

Abstract: A first-in-first-out (FIFO) memory device includes a plurality of FIFO memory cores that contain a plurality of cells. A variable cell size circuit supports user programmable cell sizes in a FIFO memory device to permit selection of a wide range of cell sizes. The variable cell size circuit controls successive accesses to a cell in the memory device, and it resets a byte count when the byte; count equals the cell size value to initialize the circuit for a subsequent access operation. The variable cell size circuit further includes a prediction circuit that indicates completion of access to the cell a predetermined number of counts prior to completion of the actual access. An alignment circuit generates data for write operations in cells that store an odd number of bytes per cell to compensate for the two byte per cell read operations. Each FIFO memory core includes a circuit that generates a cell available signal to indicate whether a cell in a corresponding FIFO memory core is available for reading.

Abstract: The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching recipes to be tuned to the differentially responsive P and N materials that form the gate.

Abstract: A method for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC remain connected to the assembly strip. The assembly strips are then passed to a test apparatus that transmits test signals to the ICs through the formed leads. The IC devices are then separated from the assembly strip using a singulation apparatus, and the separated ICs are stored in tubes for delivery. Visual inspection is also performed at various stages.

Abstract: A method for forming a localized halo implant region, comprises: implanting a first dosage of ions of a first type toward a surface of a substrate having a gate electrode formed thereon, so as to form a lightly doped region adjacent to the gate electrode; forming a disposable spacer on a sidewall of the gate electrode; forming an elevated source/drain structure adjacent to the disposable spacer; implanting a second dosage of ions of the first type toward the surface of the substrate so as to form a heavily doped region adjacent to the disposable spacer; removing the disposable spacer; and tilt-angle implanting at least one dosage of ions of a second type toward a gap created by the disposable spacer having been removed so as to form a localized halo implant region in the substrate, preferably by utilizing shadow effects of the gate electrode and the elevated source/drain structure.

Abstract: A method for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC remain connected to the assembly strip. The assembly strips are then passed to a test apparatus that transmits test signals to the ICs through the formed leads. The IC devices are then separated from the assembly strip using a singulation apparatus, and the separated ICs are stored in tubes for delivery. Visual inspection is also performed at various stages.

Abstract: An integral system for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC remain connected to the assembly strip. The assembly strips are then passed to a test apparatus that transmits test signals to the ICs through the formed leads. The IC devices are then separated from the assembly strip using a singulation apparatus, and the separated ICs are stored in tubes for delivery. Visual inspection is also performed at various stages.

Abstract: A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control the logic portion of each CAM cell. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on complementary data lines, and discharges a match line when the stored data value differs from the applied data value. The memory cell is driven using the relatively high memory operating voltage (e.g., 2.5 Volts) such that the stored charge resists soft errors. The complementary data lines and match line used to operate the comparator are driven using the relatively low logic operating voltage (e.g., 1.2 Volts) to conserve power.

Abstract: A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually refreshing data stored in the CAM array. The RAM array also stores check bits for each data word that can be generated by the EDC circuit when the data words are initially written to the CAM circuit. During the refresh operation, data words and associated check bits are read from the RAM array and transmitted to the EDC circuit. The EDC circuit analyzes each data word and associated check bits to detect errors, and corrects the data word, if necessary, before sending the data word to the CAM array.

Abstract: A method of generating a priority address using a priority encoder that includes the steps of: (1) providing a plurality of match signals from a CAM cell memory array to the priority encoder, (2) generating a most significant address bit of the priority address in response to a first set of the match signals, and (3) generating a least significant address bit of the priority address in response to the most significant address bit and a second set of the match signals. In one embodiment, step (3) is implemented by splitting the determination of the least significant address bit into two separate determinations, and the using the most significant address bit to select the result of one of these two separate determinations. Using the most significant address bit to help determine the least significant address bit significantly increases the speed of determining the least significant address bit, thereby increasing the overall speed of the priority encoder.

Abstract: A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an output hit signal with the priority encoder in response to the hit signals; (7) selecting one of the routing values as an index routing value in response to the output hit signal; and (8) routing one of the index signals as an output index value in response to the index routing value. Circuitry for implementing the method is also provided.

Abstract: A ternary CAM system includes a main memory cell configured to store complementary data signals D/D#. A first transistor has a source coupled to receive data signal D#, and a gate coupled to receive a compare signal C. A second transistor has a source coupled to receive data signal D, and a gate coupled to receive complementary compare signal C#. A third transistor has a gate coupled to drain regions of the first and second transistors. A mask cell storing a mask value is coupled to the source of the third transistor. A pre-charged match line is coupled to the drain of the third transistor. If compare signals C/C# match data signals D/D#, then the third transistor is turned off, thereby isolating match line and mask cell. If compare signals C/C# don't match data signals D/D#, then the third transistor is turned on, thereby coupling mask cell and match line.

Abstract: A vision system that compares the captured images of a die and a lead frame loaded in a die bonding apparatus with stored images thereof, and interrupts the die bonding process when the captured images fail to match the stored images. The images are directed to distinctive features of the die (e.g., the positioning and size of the die bonding pads) and lead frame (e.g., positioning and size of the leads) that differ between various die and lead frames having similar sizes. A first camera captures the lead frame image, and a second camera captures the die image. The captured die and lead frame images are digitized and passed to a computer, which compares the captured images with previously stored images. When a mismatch is detected, the computer generates an error signal that shuts down the die bonding apparatus.

Abstract: A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.

Abstract: The method of forming a photoresist pattern defining a contact hole. A photoresist pattern that defines an opening therethrough is provided over a semiconductor substrate surface. Then, a layer of water-soluble organic over-coating material (WASOOM) is coated over the photoresist pattern including the opening thereof. Next, the resulting structure is flowed to shrink the size of the opening. After the resist reflow, WASOOM is removed. Thus, using the methods of the present invention, a photoresist pattern capable of forming a 0.18 &mgr;m (and below) contact hole can be formed using an inexpensive conventional optical lithography system. Further, because WASOOM is water-soluble, WASOOM can be substantially completely removed from the photoresist pattern using a simple cleaning process, i.e., water rinse, after baking for resist reflow. Thus, the process steps are simplified and the problems such as the difficulty in CD control and the environmental issues are avoided.

Abstract: A CAM circuit including a RAM array, a CAM array, and a control circuit that systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually restoring data that has been corrupted by radiation. The RAM and CAM arrays can be formed on the same substrate, but are preferably fabricated on separate substrates and mounted in a single package or on a PCB. Both the CAM and RAM can be formed using any conventional memory type (e.g., SRAM, DRAM, NVRAM), and the CAM array can be a binary, ternary, or quad CAM array. The CAM and RAM arrays can be formed on different substrates, or the same substrate. A system including an SRAM ternary CAM array and a RAM array perform quad CAM functions by performing read functions utilizing only the RAM array, while performing lookup functions using the ternary CAM array.

Abstract: A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.

Abstract: A current tail circuit and method for a differential transistor pair affords the capability of sensing an input differential signal having a low common mode voltage when using, for example, an NMOS differential transistor pair. A current source device and a capacitor may be employed to provide at the common node of the differential transistor pair what appears to be a constant current source connected to a “negative voltage.” In one embodiment particularly useful when using an NMOS differential pair, one terminal of a capacitor is precharged to VDD and the other terminal is precharged to VSS (i.e., ground). When the amplifier needs to sense its differential input signal, a control signal turns off precharge transistors and couples the capacitor terminal previously precharged to VSS to the common-source node of a differential transistor pair.