Abstract: A current tail circuit and method for a differential transistor pair affords the capability of sensing an input differential signal having a low common mode voltage when using, for example, an NMOS differential transistor pair. A current source device and a capacitor may be employed to provide at the common node of the differential transistor pair what appears to be a constant current source connected to a “negative voltage.” In one embodiment particularly useful when using an NMOS differential pair, one terminal of a capacitor is precharged to VDD and the other terminal is precharged to VSS (i.e., ground). When the amplifier needs to sense its differential input signal, a control signal turns off precharge transistors and couples the capacitor terminal previously precharged to VSS to the common-source node of a differential transistor pair.

Abstract: A circuit and method for reading and writing to a microprocessor's internal cache memory during a test mode of operation. During write accesses, an external data bus transmits to an internal data bus an address, cache tags and data in accordance with an external clock. During read accesses, the external data bus transmits an address and receives from the internal data bus data and cache tags. In one embodiment, during a write access, the external data bus is time-multiplexed to transmit an address, cache tags and data in two clock periods of the external clock the external data bus is time-multiplexed to transmit to the internal data bus an address in the first clock period of the external clock signal and to receive tag and data in the next successive clock periods of the external clock signal. In this embodiment, reserved pins are used to specify a cache access mode, including a test mode of operation.

Abstract: A sense amplifier includes a first transistor coupled between a match line of a CAM array and a VDD supply terminal. The match line is pre-charged through the first transistor to a voltage equal to a reference voltage minus the first transistor threshold voltage, VT1. The match line is coupled to the source of a second transistor, which has a threshold voltage VT2, wherein VT2>VT1. A dummy line of the CAM array, which is coupled to the gate of the second transistor, is pre-charged to the reference voltage. A storage node, which is coupled to the drain of the second transistor, is pre-charged to the VDD supply voltage. A non-match condition causes the voltage on the match line to be pulled down. When the voltage on the dummy line exceeds the voltage on the match line by VT2, the second transistor turns on, thereby pulling down the storage node.

Abstract: An input buffer for use in an integrated circuit having a VCC voltage supply and a VSS voltage supply. The input buffer includes a p-channel field effect transistor (FET) having a source region coupled to the VCC voltage supply, a drain region coupled to a bias circuit, and a gate electrode coupled to an input terminal. The bias circuit maintains a voltage at the drain region of the p-channel FET which is slightly greater than the VSS supply voltage when a logic high voltage is applied to the input terminal. In an alternate embodiment, the input buffer includes an n-channel FET having a drain region coupled to the VCC voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. The bias circuit maintains a voltage at the source of the n-channel FET which is greater than the VSS supply voltage when a logic low voltage is applied to the input terminal.

Abstract: Physical vapor deposition (PVD) system comprises a chamber, an upper shield and a lower shield mounted within the chamber, a cover ring having one or more tabs extending radially inwardly therefrom. The PVD system further includes a shutter disk having one or more notched areas formed in the periphery thereof to receive non-contactingly the one or more tabs of the cover ring. The cover ring has two or more recesses formed in an upper side thereof with a guide pin extending from the center of the recesses. The lower shield has two or more cups with a hole therein to be engaged with the guide pin of the cover ring to keep the lower shield from rotating with respect to the cover ring. The cups of the lower shield are inserted into the recesses of the cover ring. These improvements enable a standard shutter arm assembly and a shutter disk to be utilized in a two-tab block-out scheme.

Abstract: A CAM cell including three-transistor (3T) or four-transistor (4T) DRAM cells. Data is stored using intrinsic capacitance of each 3T or 4T DRAM cell, and is applied to the gate terminal of a pull-down transistor. Read operations are performed in the 3T and 4T DRAM cells without disturbing the stored data value by applying the stored data value to the gate terminal of a pull-down transistor and detecting the operating state (i.e., turned on or turned off) of a pull-down transistor, thereby avoiding the charge sharing problems associated with 1T DRAM cells.

Abstract: A device takes as input an input bit stream and produces as output an output bit stream. A linear feedback shift register (LFSR) operates on the input bit stream and modifies the internal state of the LFSR if and only if a current bit value of the input bit stream differs from an immediately previous bit value of the input bit stream. A condenser having a compression factor N, operates on the input bit stream independently and asynchronously from the LFSR. The condenser produces a condensed value of the input bit stream. The condenser has a checksum register; a checksum accumulator register; and an adder for adding bits from the input bits stream to the checksum register. The low-order bit of the checksum register is shifted into the checksum accumulator register every N bits, and the condensed value produced by the condenser is the value in the checksum accumulator register.

Abstract: Methods for forming nitrided oxides in semiconductor devices by rapid thermal oxidation, in which a semiconductor substrate having an exposed silicon surface is placed into a thermal process chamber. Then, an ambient gas comprising N2O and an inert gas such as argon or N2 is introduced into the process chamber. Next, the silicon surface is heated to a predefined process temperature, thereby oxidizing at least a portion of the silicon surface. Finally, the semiconductor substrate is cooled. An ultra-thin oxide layer with uniform oxide characteristics, such as more boron penetration resistance, good oxide composition and thickness uniformity, increased charge to breakdown voltage in the oxide layer, can be formed.

Abstract: A level-shifting signal buffer contains a totem pole arrangement of MOS transistors connected to an output thereof and a control circuit that drives the totem pole arrangement of MOS transistors in a preferred manner so that none of the signals across the MOS transistors exceed predetermined limits that may damage the MOS transistors. A preferred signal buffer may include a PMOS pull-up transistor and an NMOS pull-down transistor arranged within a transistor totem pole. This transistor totem pole extends between a first power supply signal line that receives a first power supply signal (e.g., Vddext) and a reference signal line that receives a reference signal (e.g., GND). The PMOS pull-up transistor may be configured to support a maximum gate-to-drain voltage which is less than a difference in voltage between the first power supply signal and the reference signal.

Abstract: A quad data rate RAM (100) in accordance with the invention is a burst synchronous RAM with separate data buses (Data-In, Data-Out) for read and write data. Data can be transferred on both buses and on both the rising and the falling edge of the clock (CLK). Operating at the maximum throughput, four data items are transferred per clock cycle. In one embodiment, data is written to or read from the RAM in bursts of four data items. The RAM includes four independent internal RAM blocks (44-47). in a write burst, (i) a write address, (ii) control signal(s), and (iii) four write data items are sequentially presented to the respective four internal RAM blocks at the respective four clock edges of two consecutive clock cycles. A read burst is carried out similar to a write burst except that there is a one clock cycle latency between the four read data items and the burst address.

Abstract: A self-aligned via between interconnect layers in an integrated circuit, and a process for forming such a via which allows a less precise masking alignment to be used to fabricate an integrated circuit with increased packing density.

Abstract: A four-state (quad) CAM cell that stores one of four logic values: a logic high value, a logic low value, a logic high don't care value, and a logic low don't care value. Each quad CAM cell includes a first memory cell, a second memory cell, a comparator circuit, and a control switch. The first memory cell stores a data value (i.e., logic high value or logic low value), and transmits this stored data value to the comparator circuit. The second memory cell stores a care/don't care data value that is transmitted to the control switch. Portions of the comparator circuit and the control switch form a discharge path between a match line and a discharge line connected to the quad CAM cell. The control switch is controlled by the care/don't care value to open/close a first part of the discharge path. The comparator circuit is controlled to open a second part of the discharge path when, for example, the stored data value is equal to an applied data value.

Abstract: Preferred memory devices include a first bit line within a first block of memory and a second bit line within a second block of memory. The first bit line is electrically coupled to a reference voltage signal line by a pull-up transistor that turns on in response to an active first bit line pull-up signal (e.g., /BLPU_IOn=0). The second bit line is also electrically coupled to the reference voltage signal line by a pull-up transistor that turns on in response to an active second bit line pull-up signal (e.g., /BLPU_IOn+1=0). A control circuit is provided and this control circuit is responsive to a multi-bit shift signal. The control circuit disables generation of the active first bit line pull-up signal in favor of an active second bit line pull-up signal when a value of the shift signal designates replacement of the first block of memory with the second block of memory.

Abstract: A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal.

Abstract: A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. An exemplary 18 MBit memory array integrated circuit includes four banks of arrays and a write queue for storing at least one pending write cycle. At least a portion of the address information associated with a pending internal write operation is compared to corresponding address information associated with a subsequently-received write cycle request to determine whether a first group of memory cells to be otherwise written by the pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation.

Abstract: Integrated circuit output buffers include primary and secondary pull-down transistors and an output signal line electrically coupled to a drain of the primary pull-down transistor and a drain of the secondary pull-down transistor. A preferred control circuit is also provided. The control circuit turns on the primary pull-down transistor during first and second consecutive portions of a pull-down time interval and uses a signal fed back from the output signal line to control the timing of when a gate of the secondary pull-down transistor is electrically connected to a drain of the secondary pull-down transistor during the first portion of the pull-down time interval and also control the timing of when the gate electrode of the secondary pull-down transistor is electrically connected to a source of the secondary pull-down transistor during the second portion of the pull-down time interval.

Abstract: An encryption device has a random number generator whose output is combined by exclusive-or with plaintext input which has been encrypted by a first block cipher. The combined exclusive-or output is encrypted with a second block cipher mechanism which produces a second enciphered output. The output of the random number generator is also encrypted by a third block cipher mechanism which produces a third enciphered output. The first and second block cipher mechanisms differ from each other.

Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.

Abstract: A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Abstract: In a multi-level interconnect structure, a fusible material fills an opening in an isolation layer disposed between two interconnect levels or between an interconnect level and a device layer. The opening which may be, for example, a contact hole or a via, may be fabricated using processes generally used to fabricate normally sized vias and contact holes. The opening has a cross-sectional area A reduced by a factor of x relative to normally sized openings. Because the fusible interlevel interconnection has a reduced cross-sectional area, a programming current develops a destructive programming current density within fusible interlevel interconnection while current densities in coupled conductors, including normally sized vias and contacts, remain within long term reliability limits. Read/write circuitry connected to the fusible interlevel interconnection supports the programming current and supports a read current.