Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.

Abstract: A method for removing noise regions in a stereo 3D image, which includes a first eye image and a second eye image is achieved by calculating a maximum offset value and turning a horizontal synchronization signal and a display enable signal of the CRT timing parameters.

Abstract: A method of reducing micro-scratches during tungsten CMP. Tungsten CMP with a standard tungsten slurry is first provided on the exposed surfaces of a tungsten plug and a IMD layer on a semiconductor substrate. The tungsten CMP with an oxide slurry is then provided on the polished surfaces of the tungsten plugs and the IMD layer.

Abstract: A digital-to-analog converting method operating under two clock signals of different periods is disclosed. The method includes steps of monitoring a phase relationship between the two clock signals; starting transmission of a plurality of pre-stored series of waveform samples in response to each rising edge of the first clock signal, wherein a phase difference is present between every two adjacent series of waveform samples; outputting the waveform samples of each series in response to rising edges of the second clock signal; and selecting one of the plurality of pre-stored sets of waveform samples to be converted into an analog signal according to the phase relationship. The various pre-stored series of waveform samples having therebetween phase differences are optionally used for phase compensation so as to reduce the clock jitter between the two clock signals. A digital-to-analog converter for implementing the above-mentioned method is also disclosed.

Abstract: All memory commands are classified into two categories: background commands and foreground commands, depending on whether they are data related or not. The pointed background command and foreground commands are issued onto the DRAM bus at the earliest time when the required constrains are met. The background and foreground FSM controllers work in a pipelined or overlapped manner.

Abstract: The present invention is to provide a culling method, used in the computer graphics systems, for determining the visibility of two adjacent polygons of a polyhedron at the same time. It also provides a culling apparatus, which uses the method to execute the culling test. The culling apparatus comprises one multiplier, three multiplexers, two registers, one adder/subtractor, and a controller with a set of instructions to control the whole procedure.

Abstract: This method of prevention of particle pollution in a pre-clean chamber includes an oxygen gas supplying step for injecting oxygen gas into the pre-clean chamber; and a plasma generating step for ionizing the oxygen gas into plasma so as to interact with silicon-rich oxide to form a silicon oxide layer in the pre-clean chamber. The method according to the invention could prevent particle pollution due to peeling-off of silicon-rich oxide in a pre-clean chamber so as to prolong the life of a bell-jar therein.

Abstract: There are many validity tests, such as a depth test, used to determine which pixels are valid or invalid in a 3D computer graphic rendering process. It is not necessary to display the invalid pixels on the screen, because these pixels are hidden behind other objects or other windows. The invalid pixels will eventually be discarded in the rendering process later. Conventional designs pushed pixels into a frame buffer, no matter these pixels pass the validity tests or not. The present invention presents a pipelined bubble squeezer to separate pixels into a valid group and a invalid group. The pixels in the invalid group are not pushed into the frame buffer for achieving a better performance. The pipelined bubble squeezer behaves like many bubbles floating up to the top eventually through an interconnection network of cells.

Abstract: In order to determine the position of an object within an area viewed by a single detector of an array, signals from detectors adjacent to the single detector are compared with each other and/or the single detector. The method can be extended to larger objects to ascertain the locations of edges.

Abstract: A bond pad structure and a method of fabricating such structure are disclosed in the invention. The bond pad structure is formed over a predetermined area defined on a semiconductor substrate. The bond pad structure includes at least two metal layers formed over the predetermined area and at least one sub-structure combination layer which each is formed over the predetermined area and formed between two corresponding first metal layers. Each sub-structure combination layer includes a dielectric layer formed over the predetermined area, formed-through via openings with special disposition on the dielectric layer, a first diffusion barrier layer formed over the dielectric layer and the sidewalls and bottom of the via openings, a metal material filled into the via openings to form via plugs, and a second diffusion barrier layer formed over the first diffusion barrier layer and via plugs.

Abstract: Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Abstract: A method of measuring the width of bottom under cut includes forming spacers around an oxide line pattern and determining the width of the tail ends of the spacers that are removed along with the bottom under cut. An oxide line pattern is first formed on a substrate and a deposition layer is then deposited thereon. The deposition layer is etched to form a deposition pattern by using a photoresist pattern as a mask. A spacer is also formed against each side wall of the oxide line pattern as a result of the etching process. The etching is continued to under cut the deposition pattern and remove the tail ends of the spacers. By measuring the width of the photoresist pattern, the width of the spacer before and after the tail end is removed during each respective step, the width of the bottom under cut can be determined.

Abstract: A method for rapid preventing particles in a pre-clean chamber according to the invention includes a silica material supply step for providing a silica material in the pre-clean chamber, a gas supply step for providing oxygen gas and sputtering gas into the pre-clean chamber, and a plasma generating step for ionizing the oxygen gas and the sputtering gas by RF to form plasma and then impacting the plasma onto the silica material, so that the silica dislodged from the silica material and it reacts with the ionized oxygen at a time so as to form a silicon oxide layer rapidly on the bell-jar in the pre-clean chamber. The method of the invention prevents the silicon-rich oxide from peeling quickly so as to extend the life of the bell-jar.

Abstract: A method for fabricating a polysilicon capacitor. The method includes the following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is patterned to concurrently form a first polysilicon line and a second polysilicon line. The second polysilicon line defines a polysilicon capacitor region and is used as a lower electrode of the polysilicon capacitor. Next, an insulating layer is formed conformably on the substrate, the first polysilicon line, and the second polysilicon line. A first dielectric layer is formed on the insulating layer, which is then subjected to planarization treatment such that the planarization treatment ends up to the insulating layer. Finally, a third polysilicon line is formed on the insulating layer in the polysilicon capacitor region such that the third polysilicon line is used as an upper electrode of the polysilicon capacitor.

Abstract: The present invention provides a termination circuit with voltage-independent characteristics. The termination impedance circuit provided is coupled to a transmission line from a driver circuit. The termination impedance circuit includes a transistor-type resistor of a size A, and an impedance compensation circuit. The transistor-type resistor of a size A is operative to receive a first control signal and has a node coupled to the transmission line. The impedance compensation circuit includes a pair of transistors and a transistor of size B. The ratio of (A/B) is such that a substantial constant output impedance is achieved as large pull-down or pull-up voltage excursion at the transmission line occurs.

Abstract: A graphics system minimizes the idle time of a host processor while sending a large amount of graphics instructions in a graphics system. The graphics system includes a host processor, a system memory, a graphics memory and a graphics accelerating device (GAD) that interconnects the host processor and the graphics memory. The host processor divides the graphics instructions into graphics commands and graphics data and temporarily stores the graphics data in the system memory. The GAD receives the graphics commands coming from the host processor and receives the graphics data coming from the system memory, respectively, and sends the processed outcome to the graphics memory. Due to the graphics data being temporarily stored in the system memory, the host processor will not be idle even though many consecutive 3D graphics instructions are sent from the host processor to the GAD.

Abstract: A metal capacitor in damascene structures is provided. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire.

Abstract: An apparatus for reducing an electrical noise inside a ball grid array package is disclosed. The apparatus mainly comprises a substrate, a plurality of solder balls and a plurality of inside-connected capacitors. The substrate includes a contact layer, a power plane and a ground plane. The plurality of solder balls are fixed on the contact layer. The plurality of inside-connected capacitors are fixed on the contact layer, and a conductive glue is used to electrically connect the capacitors to the power plane and ground plane to reduce the electrical noise between the power plane and ground plane.

Abstract: An organic copper diffusion barrier layer having low dielectric constant is provided. The organic copper diffusion barrier layer can be applied to a dual damascene structure, which is formed between a copper wiring layer and an organic dielectric layer, to defend copper diffusion from the copper wiring layer into the organic dielectric layer. The organic copper diffusion barrier layer includes a benzocyclo polymer, which it has a benzene ring functional group that can catch copper and prevent copper diffusing into the organic dielectric layer. The problem of thermal diffusion and electro-migration can be avoided.

Abstract: This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor is composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.