Common-mode current feedback amplifiers

- Intersil Americas Inc.

Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

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Description
PRIORITY CLAIMS

This application claims priority under 35 U.S.C. 119(e) to the following provisional applications, each of which is incorporated herein by reference: U.S. Provisional Patent Application No. 60/611,771 filed Sep. 21, 2004; and U.S. Provisional Patent Application No. 60/554,150, filed Mar. 18, 2004.

RELATED APPLICATION

This application is related to the following commonly invented and commonly assigned applications, each of which is filed the same day as the present application: U.S. patent application Ser. No. 11/082,752 entitled “Differential-Mode Current Feedback Amplifiers”; and U.S. patent application Ser. No. 11/082,422 entitled “Current Feedback Amplifiers with separate Common-Mode and Differential-Mode Inputs”.

FIELD OF THE INVENTION

Embodiments of the present invention relate to current feedback amplifiers, including common-mode current feedback amplifiers, differential-mode current feedback amplifiers, a combinations thereof.

BACKGROUND

FIG. 1A is a macro level diagram of a basic current feedback amplifier (CFA) 100. FIG. 1B, which is a high level circuit diagram, will be used to describe the basic operation of the current feedback amplifier (CFA) 100, which can be modeled as two ideal voltage buffers 106 and 108, a complementary pair of current mirrors 110 and 112 and feedback and gain resistors RF and RG. When a voltage is applied to the non-inverting input 102, it is immediately buffered to the inverting input 104. Assuming a standard non-inverting op-amp configuration, this voltage causes a change in the current flowing through the feedback and gain resistors RF and RG. The input voltage buffer 106 must supply this current; therefore the current must flow through the current mirrors 110 and 112 and is duplicated, causing a ΔI to be applied to a high-impedance node 114. This current, flowing into the high impedance node 114, causes a change in voltage that is then transferred to the CFA output 116 by the second buffer 108. The key thing to focus on in this case is that the amplifier's operation depends on correctly sensing and mirroring the change in current caused by the initial change in input voltage. This creates the “current feedback” nature of the amplifier.

Referring now to FIG. 2, a symmetrical pair of CFAs, labeled 100a and 100b, are hooked up in a standard differential gain configuration to form a differential amplifier circuit 200. Standard analysis using the concept of half-circuits leads to the ability to analyze the differential circuit in terms of two signal paths, one for differential-mode signals and one for common-mode signals (hereafter referred to as DM and CM, respectively). Any arbitrary input to the amplifier circuit 200 can be expressed as a sum of DM and CM components. Half-circuits 300a and 300b are shown explicitly in FIG. 3.

It is immediately apparent that the DM and CM signal paths will have different voltage gains and different loading effects, and that therefore optimizing the amplifier circuit 200 for one of the paths will inevitably compromise optimal performance on the other path. More generally it may be desirable to send completely different signals on the DM and CM signal paths. It may also be desirable to cancel out part or all of either the CM or DM signals. Therefore, the ability to tune the CM and DM paths independently is desirable.

SUMMARY

Current feedback amplifiers (CFAs) are beneficial because they provide for a large slew rate at small supply currents, and because their bandwidths are insensitive to closed-loop gains. Embodiments of the present invention are directed to CFA circuits that generate CM currents. Embodiments of the present invention are also related to CFA circuits that generate DM currents. Further embodiments of the present invention are related to fully differential CFA circuits with separate CM and DM inputs. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and insensitive bandwidth, with independent control of DM and CM signals.

Further embodiments, and the features, aspects, and advantages of the present invention will become more apparent from the detailed description set forth below, the drawings and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a macro level diagram of a basic CFA.

FIG. 1B is a high level circuit diagram that is useful for describing the basic operation of a CFA.

FIG. 2 is a high level circuit diagram showing a symmetrical pair of CFAs hooked up in a standard differential gain configuration to form a differential configuration of two amplifiers.

FIGS. 3A and 3B are high level circuit diagrams of two half-circuits that provide the ability to analyze the differential circuit of FIG. 2 in terms of two signal paths, one for DM signals and one for CM signals.

FIGS. 4A and 4B are high level circuit diagrams illustrating common-mode (CM) current feedback amplifier circuits that amplify common-mode (CM) signals using the generation of CM currents.

FIG. 5 is a high level circuit diagram illustrating differential-mode (DM) current feedback amplifier circuit that amplifies differential-mode (DM) signals using the generation of DM currents.

FIG. 6 shows circuitry implementing the diagram of FIG. 4A using bipolar transistors, according to an embodiment of the present invention.

FIG. 7 shows circuitry implementing the diagram of FIG. 5 using bipolar transistors, according to an embodiment of the present invention.

FIG. 8 shows circuitry implementing a fully differential current feedback amplifier (CFA) circuit with separate common-mode (CM) and differential-mode (DM) inputs, according to an embodiment of the present invention.

FIG. 9 shows circuitry for implementing a partial cancellation differential-mode (DM) current feedback amplifier circuit, according to an embodiment of the present invention.

FIGS. 10A–10D show various circuitry for generating sums and differences of current using current mirrors.

FIG. 11 shows circuitry that generates CM and DM currents using multiple buffer currents, but with less current mirrors than shown in FIG. 8, according to an embodiment of the present invention.

FIG. 12 shows circuitry for implementing a hybrid CFA/VFA, according to an embodiment of the present invention.

 DETAILED DESCRIPTION

As mentioned above, it is a desired to have the ability to tune the CM and DM paths of an amplifier circuit independently. One possible way to address this issue is with independent compensation of DM and CM signals, as described in U.S. patent application Ser. No. 10/657,447, entitled “Common-Mode and Differential-Mode Compensation for Operational Amplifier Circuits,” filed Sep. 8, 2003, which is incorporated by reference herein. The aforementioned Patent Application addresses the problem of CM vs. DM stability, but does not explicitly provide for separate control of the DM & CM voltages.

A more effective and traditional scheme is to use a fully differential op-amp architecture. An example of such an approach would be the standard folded-cascode voltage-feedback differential amplifier. However, the standard folded-cascode voltage-feedback differential amplifier does not provide the unique advantages of a CFA architecture, such as insensitivity of bandwidth to closed-loop gain and large slew rate at small supply currents.

In order to make a CM or DM current-feedback loop, by definition there should exist the ability to generate currents that are proportional to either the sum or difference of the input signals. These currents then become the inputs to the current mirrors of a CFA configuration. Adding and subtracting currents is possible with the use of parallel currents and current mirrors. FIGS. 4A and 5 are high level circuit diagrams illustrating how the CM and DM currents can be generated, in accordance with embodiments of the present invention. Implementations of FIGS. 4A and 5 are discussed below, respectively, with reference to FIGS. 6 and 7. Other implementations are also within the spirit and scope of the present invention.

Referring now to FIG. 4A, input voltage buffers 406a and 406b of two CFAs 400a and 400b are configured such that supply currents are split into two equal parts. The CFA 400a includes an input voltage buffer 406a, a pair of current mirrors 410a and 412a, and an output buffer 408a. When a voltage is applied to a non-inverting input 402a of the input voltage buffer 406a, it is immediately buffered to an inverting input 404a. A feedback resistor RF connects the OUTA to IN−A (in a similar fashion as shown in FIG. 1B), and a feedback resistor RF connects the OUTB to IN−B. Assuming a standard non-inverting op-amp configuration, this voltage causes a change in the current flowing through the feedback resistors, and optional gain resistors. The input voltage buffer 406a must supply this current; therefore it must flow through current mirrors 410a and 412a and is duplicated, causing a ΔI to be applied to a high-impedance node 414a. This current, flowing into the high impedance node 414a, causes a change in voltage that is then transferred to a first output 416a (OUTA) by an output buffer 408a. CFA 400b, which includes elements labeled in a similar manner (but with the suffix “b” instead of “a”) operates in a similar manner to CFA 400a. Also shown in FIG. 4A are optional gain resistors RG.

By wiring ½ of the supply current IA of buffer 406a in parallel with ½ of the supply current IB from the opposite buffer 406b, a CM current is generated. Explicitly, with the inputs denoted A and B, and the current generated by the two inputs buffers 406a and 406b labeled IA and IB, respectively, then the current sensed by each of the CFA's 400a and 400b can be expressed as ICM=½(IA+IB). This is the definition of a CM signal; if A and B are equal then ICM=IA=IB, whereas if A and B are DM, that is to say equal in magnitude but opposite in phase, IA=−IB and ICM=0. Accordingly, the circuit of FIG. 4A admits and amplifies CM signals, and rejects DM signals. The various currents generated by each input buffer 406a and 406b, such as ½(IA+IB), are proportional to a difference between an input voltage signal provided to a non-inverting input of the amplifier circuit (formed by the input buffer) and a fraction of its associated output voltage signal.

The circuit of FIG. 4A shows two single-ended inputs, labeled IN+A and IN+B, that will in general not be equal to each other. Therefore, there may be a DM signal that needs to be cancelled out in order to provide CM operation. However, a CM input signal can be guaranteed by shorting together input nodes 402a (IN+A) and 402b (IN+B). By doing so, the two independent inputs are replaced with a single input which is inherently CM. In such a case, the currents and voltages of the CFA 400a and the CFA 400b would be identical, and therefore portions of the circuit can be eliminated without loss of functionality. For example, the input buffer 406b can be eliminated. This may be desirable in order to reduce the design's complexity and cost. The resulting circuit, with input buffer 406b eliminated, is shown in FIG. 4B.

Referring now to FIG. 5, in a similar manner as in FIG. 4A, input voltage buffers 506a and 506b of two CFAs 500a and 500b are configured such that supply currents are split into two equal parts. The various currents generated by each input buffer 506a and 506b, such as ½ IA, are proportional to a difference between an input voltage signal provided to a non-inverting input of the amplifier circuit (formed by the input buffer) and a fraction of its associated output voltage signal. FIG. 5 demonstrates the generation of DM currents by using current mirrors to invert ½ of the buffer current before it is added together. This means that the current sensed can now be expressed as IDM=½ (IA−IB). When A and B are CM, then IDM will equal zero, whereas when A and B are DM, IA=−IB and therefore IDM=IA=−IB. Accordingly, the circuit of FIG. 5 admits and amplifies DM signals, and rejects CM signals. In the specific embodiment shown in FIG. 5, eight current mirrors 510a, 520a, 512a, 522a, 510b, 520b, 522b and 512b are used. A first group of the current mirrors (i.e., current mirrors 510a, 512a, 510b and 512b) are used for adding currents together, and providing the added currents to high impedance nodes (i.e., nodes 514a and 514b). A second group of the current mirrors (520a, 522a, 520b and 522b) are used to provide mirrored versions of currents to the first group of current mirrors where they can be added as appropriate. A feedback resistor RF (not shown, for simplicity) connects the OUTA to IN−A (in a similar fashion as shown in FIG. 1B and 4A), and a feedback resistor RF (not shown, for simplicity) connects the OUTB to IN−B.

FIGS. 6 and 7 show implementations, according to embodiments of the present invention, of the concepts of FIGS. 4A and 5, respectively. Bipolar transistors and non-degenerate current mirrors are used for simplicity. However, it is within the scope of the present invention that the bipolar transistors shown in the Figures can be replaced with other transistors, such as but not limited to, metal-oxide semiconductor (MOS), metal semiconductor (MES) or field effect (FET) transistors with similar behavior. Additionally, the use of alternative types of current mirrors are within the spirit and scope of the present invention, as would be appreciated by one or ordinary skill in the art.

Referring to FIG. 6, the input voltage buffer 406a is shown as including NPN transistor Q2a and PNP transistor Q4a having common bases forming the non-inverting input IN+A of the input voltage buffer 406a, which is applied to the non-inverting input IN+A of the CFA 400a. The NPN transistor Q2a has its collector connected to a power supply rail Vcc, and its emitter connected through a current source I2a to a power supply rail Vee. The PNP transistor Q4a has its collector connected to the power supply rail Vee, and its emitter connected through a current source I1a to the power supply rail Vcc. The emitters of NPN transistor Q8a and PNP transistor Q12a form the output 404a of the input voltage buffer 406a, which is applied to the inverting input IN−A of the CFA 400a. NPN transistor Q8a and PNP transistor Q12a are connected in an emitter follower configuration with the collector of transistor Q8a connected to an input terminal of the current mirror 410a, and the collector of transistor Q12a connected to an input terminal of the current mirror 412a. The outputs of the current mirrors 410a and 412a are connected to form the gain node 414a. The gain node 414a is connected to an input of the output buffer 408a. The output 416a of the output buffer 408a forms the output OUTA of the CFA 400a.

The input voltage buffer 406a also includes NPN transistor Q6a and PNP transistor Q10a, which are connected in a similar manner as transistors Q8a and Q12a. More specifically, NPN transistor Q6a and PNP transistor Q10a are also connected in an emitter follower configuration, with their emitters connected to the emitters of transistors Q8a and Q12a, which form the inverting input IN−A of the CFA 400a. However, rather than the collectors of transistors Q6a and Q10a being connected, respectively, to the inputs of current mirrors 410a and 412a, the collector of transistor Q6a is connected to the input of current mirror 410b, and the collector of transistor Q10a is connected to the input of current mirror 412b. In the above manner, the collector of transistor Q8a provides ½ IA to the input of current mirror 410a, which also receives ½ IB provided by the collector of transistor Q6b. The collector of transistor Q6a provides ½ IA to the input of current mirror 410b, which also receives ½ IB provided by the collector of transistor Q8b.

The input voltage buffer 406b, which provides the non-inverting input IN+B and the inverting input IN−B, includes a similar topology as buffer 406a. Accordingly, buffer 406b is labeled in the same manner as buffer 406a (except the suffix “a” is replaced with the suffix “b”), and thus need not be described in additional detail. As mentioned above, alternative topologies for the buffers can be used, while still being within the scope of the present invention.

The current mirror 410a is shown as including PNP transistors Q14a and Q16a having their bases connected together and their emitters connected together. The collector of transistor Q14a, which is connected to its base, forms an input of the current mirror 410a. The collector of transistor Q16a forms an output of the current mirror 410a. In this embodiment, the input of the current mirror 410a receives current ½ IA from input voltage buffer 406a, and current ½ IB from input voltage buffer 406b, and thus receives ½ (IA+IB), and provides that current to high impedance node 414a. The other current mirrors 410b, 412a and 412b are shown as being implemented in a similar manner, and thus need not be described in detail. As mentioned above, alternative topologies for the current mirrors can be used, while stilling being within the scope of the present invention. The operation of the circuit of FIG. 6 was described above in the description of FIG. 4A.

Referring now to FIG. 7, the input voltage buffers 506a and 506b are shown as being implemented in a similar manner as buffers 406a and 406b in FIG. 6, and are thus labeled in a similar manner. Further, current mirrors 510a, 512a, 510b, and 512b are shown as being implemented in a similar manner as currents mirrors 410a, 412a, 410b and 412b, and thus are labeled in a similar manner. The remaining current mirrors 520a, 522a, 520b and 522b are also shown as being implemented in a similar manner, and thus need not be described in additional detail. The operation of the circuit of FIG. 7, was described above in the description of FIG. 5.

Embodiments of the present invention are also directed to combinations of the CM and DM types of current generators that were described above with reference to FIGS. 4–7. These current generators can be combined, in accordance with embodiments of the present invention, to obtain whatever mix of CM and DM control desired. Below, there is a discussion of specific architectures that can be obtained, in accordance with embodiments of the present invention.

Architectures and Implementations

Embodiments of the present invention are also directed to architectures that include combinations of current feedback, voltage feedback, CM and DM signals. Embodiments of the present invention are also directed to implementations of such architectures. In the implementations described below, bipolar transistors are shown. However, alternative types of transistors, such as but not limited to, metal-oxide semiconductor (MOS) or metal semiconductor (MES) transistors with similar behavior, can be used, and are thus within the spirit and scope of the present invention, as would be appreciated by one or ordinary skill in the art. As with FIGS. 5–7, for simplicity, the external feedback and gain resistors are not shown in FIGS. 8–10.

The Fully Differential CFA

By implementing two independent input stages, one using the CM current-generating strategy and the other using the DM current generator strategy, the generated currents can be added together to create classic fully differential functionality, where the DM and CM can be independently and simultaneously controlled.

FIG. 8 demonstrates a straightforward implementation of a fully differential CFA circuit, including DM input buffers 806a and 806b, output buffers 808a and 808b, current mirrors 810a, 812a, 820a, 822a, 810b, 812b, 820b and 822b, and an independent CM input buffer 806c. The input buffers' supply current is explicitly duplicated by the use of parallel output devices, and the signal-inverting current mirrors are explicit and separate from the gain-stage mirrors of the rest of the amplifier. Note the use of simple current mirrors and buffers, but of course actual designs might use fancier topologies such as degenerated Wilson mirrors, or mirrors using emitter inputs and both sexes of transistor, etc.

As mentioned above in the discussion of FIGS. 4A and 4B, a CM input signal can be guaranteed by shorting together input nodes 402a and 402b. By doing so, the two independent inputs are replaced with a single input which is inherently CM. In such a case, the currents and voltages of the CFA 400a and the CFA 400b would be identical, and therefore portions of the circuit can be eliminated without loss of functionality to reduce the design's complexity and cost (e.g., in FIG. 4A, input buffer 406b can be eliminated). The fully differential architecture of FIG. 8 demonstrates this principle in operation. The input labeled “IN_CM” goes into the buffer 806c, which provides identical (and thus, CM) currents into both sides of the circuit. CM feedback is provided using current feedback resistors RF, which presents the output of buffer 806c with the average of the two output voltages (outputs of buffers 808a and 808b). Meanwhile, differential signals are provided by the input buffers 806a and 806b together with current mirrors 810a, 812a, 810b and 822b. The output of this circuit will be a sum of the DM and CM signals: (OUTA−OUTB)=GAIN_DM*(IN+DM−IN−DM); and ½(OUTA+OUTB)=GAIN_CM*(IN_CM), where GAIN_DM and GAIN_CM are the closed-loop gains of the differential and common mode feedback loops, respectively. The GAIN_DM and GAIN_CM are set by feedback resistors RF and optional gain resistor RG.

The “Partially Cancelled” CFA:

By using the scheme of FIG. 5, but not canceling the current 100%, the CM current signal can be attenuated with respect to the DM signal, in accordance with an embodiment of the present invention. For example, if the current mirrors used to invert the signal in FIG. 5 were to have a current gain of 2:1, rather than 1:1, then the canceling signal would be equal to ½ of ½ the input buffer current, and Itotal(A)=½IA−¼IB=¾IDM+¼ICM. Therefore, the effective transconductance and gain of the DM will about three times as much as the CM. If independent control of the CM is not required and the desire is simply to damp out an undesired CM signal, this scheme (an embodiment of which is shown in FIG. 9) is simpler and less costly to implement than the fully differential strategy mentioned above. Note that it is possible to just as easily implement partial CM so that the DM is attenuated with respect to the CM.

Referring now to FIGS. 9, the partial cancellation embodiment is shown as including input buffers 906a and 906b, multiple output current mirrors 910a, 910b, 912a and 912b, and output buffers 908a and 908b. FIG. 9 demonstrates an embodiment whereby the differential current is generated without the need for separate buffer output devices and current mirrors, thus saving component count and overall cost. Instead, the main gain mirrors of the amplifier, which now have multiple outputs, perform the task of duplicating and inverting the supply signal. The potential drawback to this embodiment is that the input currents to the gain mirrors of each amplifier are now coupled as follows:

    • I. IIN(A)=IA+K·IIN(B)
    • II. IIN(B)=IB+K·IIN(A)
    • III. Where K is the current gain of the extra output on the gain mirror

Assuming the presence of a CM signal such that IA=IB=ICM, and solving for IIN, IIN=ICM·(1+K)/(1−K2). Therefore, when total cancellation of the differential mode is attempted, K→1 and IIN→∞, which is an undesirable result. Therefore, this circuit will be limited to “partially cancelled” CFA's as described above.

More specifically, when comparing FIG. 9 to FIG. 6, it can be seen that the input buffer 906a is implemented without transistors Q8a and Q12a, and the input buffer 906b is implemented without transistors Q8b and Q12b. Thus, the currents produced by the buffer 906b are not halved, causing IA (not ½ IA) to be provided to the input of the current mirror 910a, and −IA (not −½ IA) to be provided to the input of the current mirror 912a. The various currents generated by each input buffer 906a and 906b, such as IA and IB, are proportional to a difference between an input voltage signal provided to a non-inverting input of the amplifier circuit (formed by the input buffer) and a fraction of its associated output voltage signal.

To create a second output for each current mirror, an additional transistor is added to each current mirror. For example, in current mirror 910a, a transistor Q17a is added, with its base connected to the bases of transistors Q16a and Q14a, its emitter connected to the emitters of transistors Q16a and Q14a, and its collector forming the second output of the current mirror. The first output of the current mirror 910a (the collector of transistor Q16a) outputs IA, and the second output of the current mirror 910a (the collector of transistor Q17a) outputs K·IA, where K, which is less than 1, is dependent on the size of the transistor Q17a.

Various Implementations for Generating Sums and Differences of Current

The above discussed circuit of FIG. 8 presented an implementation of a fully differential CFA architecture. Alternative schemes for generating sums and differences of currents using current mirrors are also within the scope of the present invention. Such alternative schemes use both the input & output of a mirror. FIGS. 10A–10D demonstrate various implementations of this concept. In all cases, currents combined in parallel at the input side of a current mirror add together, while currents taken away from the output side serve to subtract from the total output current.

FIG. 10A presents a basic current mirror 101A, showing three currents being added together (IN1, IN2, IN3) and two currents being subtracted from the output (OUT1, OUT2). The total output current will be given approximately by:
IOUT=IN1+IN2+IN3−OUT1−OUT2

Any number of currents could be combined in such a fashion. The limitation of FIG. 10A is that the output node of the mirror (in this implementation, the collector of the output transistor Q4) may experience large variations in voltage, and this may disrupt the correct functioning of output current source OUT1, OUT2, etc.

In order to avoid this effect, a slightly more complicated current mirror 1010B with degeneration resistors (RD) attached to the emitters (of transistors Q14 and Q16), as shown in FIG. 10B, can be employed. This circuit is superior in that variations on the output voltage of the current mirror do not affect the voltage seen by the subtracting current sources at the output. Note that the input currents can be added in a similar fashion, at the emitter terminal of the input transistor Q14, as demonstrated with IN3. This circuit has the drawback that the currents through the transistors will no longer match precisely, and therefore some nonlinearity may be introduced.

This problem can be ameliorated with an additional cascode transistor Q15, as demonstrated in the modified Wilson current mirror 1010C of FIG. 10C.

Finally, both a cascode transistor Q15 on the output and degeneration resistors RD could be used, with inputs & outputs connected at a number of possible nodes as shown in the current mirror 1010D of FIG. 10D.

This is not an exhaustive list of possibilities, but shows some of the more common current mirrors typically implemented in integrated circuits. Accordingly, one of ordinary skill in the art will understand that alternative current mirror circuits can be used for adding and subtracting currents, while still being within the spirit and scope of the present invention.

Alternative Fully Differential CFA

The circuit of FIG. 11 implements a fully differential CFA using cascoded Wilson current mirrors (which were discussed above with reference to FIG. 10C), in accordance with an embodiment of the present invention. Rather than using an extra set of current mirrors to generate inverted currents, as in FIG. 8, the circuit of FIG. 11 uses direct subtraction via connection to the outputs of the main gain mirrors.

The embodiment of FIG. 11 includes input buffers 1106a and 1106b, cascoded Wilson current mirrors 1110a, 1112a, 1110b and 1112b, output buffers 1108a and 1108b, and CM input buffer 1106c. FIG. 11 demonstrates an embodiment for generating CM and DM signal currents that require multiple buffer currents, but does not require additional current mirrors. The subtraction function required for DM operation is performed by taking away current from the output of the gain-node current mirrors, rather than trying to inject the correct phase into the input. The benefit is once again a reduction of the circuitry required. A second potential benefit is that this scheme may allow higher frequency operation, since there is no additional phase shift added by extra current mirror stages. A potential drawback could be that since this architecture involves connecting extra circuitry to the gain node side of the current mirrors, it could result in decreased gain and/or greater nonlinearity which should be compensated for. However, so long as these issues are appropriately addressed, FIG. 11 provides an excellent implementation.

Hybrid CFA/VFA Combinations

There is no particular reason that there is a requirement to use a CFA input for both CM and DM signals. It is possible, for example, to use the DM CFA input of FIG. 5, but generate a common-mode signal using a (somewhat modified) standard differential pair. This would make the DM a CFA, and the CM a voltage feedback amplifier (VFA). There are various reasons why this may be desirable. For example, there may be no need for the special characteristics of a CFA for the CM. For another example, it might be desirable to have a small voltage offset or bias current on the CM, or perhaps the CFA requirement for an external feedback resistor is undesirable. The VFA input might be simpler and less costly to implement. FIG. 12 shows a block diagram of such a hybrid voltage-feedback/current-feedback design.

The circuit of FIG. 12, which implements a hybrid CFA/VFA, is shown as using the simple degenerated mirrors of FIG. 10(B). It also demonstrates a voltage-controlled common-mode feedback circuit, to demonstrate that the differential and common-mode portions of the overall architecture can be combined with other types of amplifier architecture in hybrid circuits.

Referring now to FIG. 12, in this particular example the CM circuit of FIG. 10 has been replaced with a voltage feedback circuit (VFC), while the DM circuit is similar to that used in FIG. 11. The new CM circuitry performs the same task as before, namely providing identical currents to the left and right halves of the circuit. However, rather than using a voltage buffer as an input stage, the CM circuit of FIG. 12 uses a differential pair circuit 1250c. The CM current is therefore dependent on the difference between the voltage at the IN_CM input node and the voltage at a CM feedback node 1252c. This means that the CM circuit is now operating in a voltage-feedback mode rather than the current-feedback mode of FIG. 11. Of particular note in FIG. 12 is the fact that the differential pair circuit 1250c has multiple outputs. Additionally, in FIG. 12, the two pairs of outputs are connected such that at steady state, the currents will be balanced equally in both sides of the differential pair circuit 1250c, which is a desirable condition for optimal voltage-feedback operation.

Specifically, the differential pair circuit 1250c is shown as including four NPN transistors labeled Q52c, Q54c, Q56c and Q58c. The bases of transistors Q52c and Q54c are connected together and form the CM input (CM_IN) 1202c. The emitters of transistor Q52 and Q54, which are connected together, are connected through a current source Ic to the rail voltage VEE. The bases of transistors Q56c and Q58c, which are connected together, form a second input 1204c of the differential pair circuit 1250c, which is connected to OUTA and OUTB by feedback resistors RF. The bases of transistors Q56c and Q58c, which are connected together, are connected through the current source Ic to the rail voltage VEE. Transistors Q52c and Q54c provide the CM voltage-feedback current, while transistors Q56c and Q58c remove CM current from (or provide a current of opposite polarity to) the high-impedance nodes 1214a and 1214b, and therefore at steady state the current through all four transistors Q52c, Q54c, Q56c and Q58c should be equal. One of ordinary skill in the art would appreciate that the differential pair circuit 1250c could be implemented in other manners that are also within the spirit and scope of the present invention.

For convenience, identical or similar components in the various Figures have been labeled in a similar manner (i.e., the last two number are the same). For example, one of the input buffers is labeled 406a in FIGS. 4 and 6, 506a in FIGS. 5 and 7, 806a in FIG. 8, 906a in FIG. 9, 1106a in FIG. 11, and 1206a in FIG. 12. For another example, one of the high impedance nodes is labeled 414a in FIGS. 4 and 6, 514a in FIGS. 5 and 7, 814a in FIG. 8, 914a in FIG. 9, 1114a in FIG. 11, and 1214a in FIG. 12. This labeling is useful for understanding similarities, and differences, between the various embodiments.

The forgoing description is of the preferred embodiments of the present invention. These embodiments have been provided for the purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to a practitioner skilled in the art. Embodiments were chosen and described in order to best describe the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention. Slight modifications and variations are believed to be within the spirit and scope of the present invention. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims

1. A common-mode current feedback amplifier circuit, comprising:

a first input buffer (406a) having an input (402a) forming a first non-inverting input (IN+A) of the amplifier circuit, and an output (404a) forming a first inverting input (IN−A) of the amplifier circuit, the first input buffer (406a) producing a first current (½ IA), a second current (½ IA), a third current (−½ IA), and a fourth current (−½ IA);
a second input buffer (406b) having an input (402b) forming a second non-inverting input (IN+B) of the amplifier circuit, and an output (404b) forming a second inverting input (IN−B) of the amplifier circuit, the second input buffer (406b) producing a fifth current (½ IB), a sixth current (½ IB), a seventh current (−½ IB), and an eighth current (−½ IB);
a first current mirror (410a) receiving the first and the sixth currents, and providing a current proportional to a sum of the first and the sixth currents (½ (IA+B)) to a first high impedance node (414a);
a second current mirror (412a) receiving the third and the eighth currents, and providing a current proportional to a sum of the third and eighth currents (−½ (IA+IB)) to the first high impedance node (414a);
a third current mirror (410b) receiving the fifth and the second currents, and providing a current proportional to a sum of the fifth and second currents (½ (IB+IA)) to a second high impedance node (414b);
a fourth current mirror (412b) receiving the seventh and the fourth currents, and providing a current proportional to a sum of the seventh and fourth currents (−½(IB+IA)) to the second high impedance node (414b); and
a first output buffer (408a) having an input and an output (416a), the input connected to the first high impedance node (414a), and the output (416a) forming a first output (OUTA) of the amplifier circuit; and
a second output buffer (408b) having an input and an output (416b), the input connected to the second high impedance node (414b), and the output (416b) forming a second output (OUTB) of the amplifier circuit.

2. The amplifier circuit of claim 1, wherein:

the first current (½ IA), the second current (½ IA), the third current (−½ IA), and the fourth current (−½ IA) are proportional to a difference between an input voltage provided to the first non-inverting input (IN+A) of the amplifier circuit and a fraction of its associated output voltage at the first output (OUTA); and
the fifth current (½ IB), the sixth current (½ IB), the seventh current (−½ IB), and the eighth current (−½ IB) are proportional to a difference between an input voltage provided to the second non-inverting input (IN+B) of the amplifier circuit and a fraction of its associated output voltage at the second output (OUTB).

3. The amplifier circuit of claim 1, wherein a feedback resistor connects the first output (OUTA) of the amplifier circuit to the first inverting input (IN−A) of the amplifier circuit.

4. The amplifier circuit of claim 3, wherein a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the second inverting input (IN−B) of the amplifier circuit.

5. The amplifier circuit of claim 1, wherein the input (402a) of the first input buffer (406a) is connected to the input (402b) of the second input buffer (406b).

6. The amplifier circuit of claim 1, wherein the first input buffer (406a) comprises:

a first transistor (Q2a) including a base, a collector connected to a first voltage rail (VCC), and an emitter;
a second transistor (Q4a) including a base connected to the base of the first transistor (Q2a), a collector connected to a second voltage rail (VEE), and an emitter;
a third transistor (Q8a) including a base connected to the emitter of the second transistor (Q4a), a collector connected to an input of the first current mirror (410a), and an emitter;
a fourth transistor (Q12a) including a base connected to the emitter of the first transistor (Q2a), a collector connected to an input of the second current mirror (412a), and an emitter;
a fifth transistor (Q6a) including a base connected to the base of the third transistor (Q8a), a collector connected to an input of the third current mirror (410b), and an emitter connected to the emitter of the third transistor (Q8a);
a sixth transistor (Q10a) including a base connected to the base of the fourth transistor (Q12a), a collector connected to an input of the fourth current mirror (412b), and an emitter connected to the emitter of the fourth transistor (Q12a);
a first current source (I1a) connected between the first voltage rail (VCC) and the emitter of the second transistor (Q4a);
a second current source (I2a) connected between the second voltage rail (VEE) and the emitter of the first transistor (Q2a);
wherein the first and third transistors (Q2a, Q8a) are a first type of transistor, and the second and forth transistors (Q4a, Q12a) are a second type of transistor;
wherein the bases of the first and second transistors (Q2a, Q4a) form the first non-inverting input (IN+A); and
wherein the emitters of the third and fourth transistors (Q8a, Q12a) form first the inverting input (IN−A).

7. The amplifier circuit of claim 6, wherein:

the first, third and fifth transistors (Q2a, Q8a, Q6a) are N-type transistors, and the second, forth transistors and sixth transistors (Q4a, Q12a, Q10a) are P-type transistors.

8. The amplifier circuit of claim 6, wherein the second input buffer (406b) comprises:

a seventh transistor (Q2b) including a base, a collector connected to a first voltage rail (VCC), and an emitter;
a eighth transistor (Q4b) including a base connected to the base of the seventh transistor (Q2b), a collector connected to a second voltage rail (VEE), and an emitter;
a ninth transistor (Q8b) including a base connected to the emitter of the eighth transistor (Q4b), a collector connected to an input of the third current mirror (410b), and an emitter;
a tenth transistor (Q12b) including a base connected to the emitter of the seventh transistor (Q2b), a collector connected to an input of the fourth current mirror (412b), and an emitter;
a eleventh transistor (Q6b) including a base connected to the base of the ninth transistor (Q8b), a collector connected to an input of the first current mirror (410a), and an emitter connected to the emitter of the ninth transistor (Q8a);
a twelfth transistor (Q10b) including a base connected to the base of the tenth transistor (Q12b), a collector connected to an input of the second current mirror (412a), and an emitter connected to the emitter of the tenth transistor (Q12b);
a third current source (I1b) connected between the first voltage rail (VCC) and the emitter of the eighth transistor (Q4b);
a fourth current source (I2b) connected between the second voltage rail (VEE) and the emitter of the fifth transistor (Q2b);
wherein the seventh, ninth and eleventh transistors (Q2b, Q8b, Q6b) are a first type of transistor, and the eighth, tenth and twelfth, transistors (Q4b, Q12b, Q10b) are a second type of transistor;
wherein the bases of the seventh and eighth transistors (Q2b, Q4b) form the second non-inverting input (IN+B); and
wherein the emitters of the ninth and tenth transistors (Q8b, Q12b) form the second inverting input (IN−B).

9. The amplifier circuit of claim 8, wherein:

the first, third, fifth, seventh, ninth, and eleventh transistors (Q2a, Q8a, Q6a, Q2b, Q8b, Q6b) are N-type transistors, and the second, forth, sixth, eighth, tenth and twelfth transistors (Q4a, Q12a, Q10a, Q4b, Q12b, Q10b) are P-type transistors.

10. A method for amplifying common-mode (CM) signals using the generation of CM currents, comprising:

receiving a first input signal at a first input buffer (406a);
receiving a second input signal at the second input buffer (406b);
using the first input buffer (406a) to produce a first current (½ IA), a second current (½ IA), a third current (−½ IA), and a fourth current (−½ IA);
using the second input buffer (406b) to produce a fifth current (½ IB), a sixth current (½ IB), a seventh current (−½ IB), and an eighth current (−½ IB);
using a first current mirror (410a) to provide a current proportional to a sum of the first and the sixth currents (½ (IA+IB)) to a first high impedance node (414a);
using a second current mirror (412a) to provide a current proportional to a sum of the third and the eighth currents (−½ (IA+IB)) to the first high impedance node (414a);
using a third current mirror (410b) to provide a current proportional to a sum of the fifth and the second currents (½ (IB+IA)) to a second high impedance node (414b);
using a fourth current mirror (412b) to provide a current proportional to a sum of the seventh and fourth currents (−½ (IB+IA)) to the second high impedance node (414b);
using a first output buffer (408a) to buffer a signal at the first high impedance node (414a) and to produce a first output (OUTA) therefrom; and
using a second output buffer (408b) to buffer a signal at the second high impedance node (414b) and to produce a second output (OUTB) therefrom.

11. The method of claim 10, wherein:

the first current (½ IA), the second current (½ IA), the third current (−½ IA), and the fourth current (−½ IA) are proportional to a difference between the first input signal and a fraction of the first output (OUTA); and
the fifth current (½ IB), the sixth current (½ IB), the seventh current (−½ IB), and the eighth current (−½ IB) are proportional to a difference between the second input signal and a fraction of the second output (OUTB).

12. A common-mode current feedback amplifier circuit, comprising:

an input buffer (406a) having an input (402a) forming a non-inverting input (IN+A) of the amplifier circuit, and an output (404a) forming an inverting input (IN−A) of the amplifier circuit, the input buffer (406a) producing a first current (½ IA), a second current (½ IA), a third current (−½ IA), and a fourth current (−½ IA);
a first current mirror (410a) receiving the first current (½ IA) from the input buffer (406a), and providing a mirrored version of the first current (½ IA) to a first high impedance node (414a);
a second current mirror (412a) receiving the third current (−½ IA) from the input buffer (406a), and providing a mirrored version of the third current (−½ IA) to the first high impedance node (414a);
a third current mirror (410b) receiving the second current (½ IA) from the input buffer (406a), and providing a mirrored version of the second current (½ IA) to a second high impedance node (414b);
a fourth current mirror (412b) receiving the fourth current (−½ IA) from the input buffer (406a), and providing a mirrored version of the fourth current (−½ IA) to the second high impedance node (414b);
a first output buffer (408a) having an input and an output (416a), the input connected to the first high impedance node (414a), and the output (416a) forming a first output (OUTA) of the amplifier circuit; and
a second output buffer (408b) having an input and an output (416b), the input connected to the second high impedance node (414b), and the output (416b) forming a second output (OUTB) of the amplifier circuit.

13. The amplifier circuit of claim 12, wherein the first current (½ IA), the second current (½ IA), third current (−½ IA), and the fourth current (−½ IA) are proportional to a difference between an input voltage provided to the non-inverting input (IN+A) of the amplifier circuit and a fraction of its associated output voltage at the first output (OUTA).

14. The amplifier circuit of claim 12, wherein a feedback resistor connects the first output (OUTA) of the amplifier circuit to the inverting input (IN−A) of the amplifier circuit.

15. The amplifier circuit of claim 14, wherein a second feedback resistor connects the second output (OUTB) of the amplifier circuit to the inverting input (IN−A) of the amplifier circuit.

16. The amplifier circuit of claim 12, wherein the input buffer (406a) comprises:

a first transistor (Q2a) including a base, a collector connected to a first voltage rail (VCC), and an emitter;
a second transistor (Q4a) including a base connected to the base of the first transistor (Q2a), a collector connected to a second voltage rail (VEE), and an emitter;
a third transistor (Q8a) including a base connected to the emitter of the second transistor (Q4a), a collector connected to an input of the first current mirror (410a), and an emitter;
a fourth transistor (Q12a) including a base connected to the emitter of the first transistor (Q2a), a collector connected to an input of the second current mirror (412a), and an emitter;
a fifth transistor (Q6a) including a base connected to the base of the third transistor (Q8a), a collector connected to an input of the third current mirror (410b), and an emitter connected to the emitter of the third transistor (Q8a);
a sixth transistor (Q10a) including a base connected to the base of the fourth transistor (Q12a), a collector connected to an input of the fourth current mirror (412b), and an emitter connected to the emitter of the fourth transistor (Q12a);
a first current source (I1a) connected between the first voltage rail (VCC) and the emitter of the second transistor (Q4a);
a second current source (I2a) connected between the second voltage rail (VEE) and the emitter of the first transistor (Q2a);
wherein the first and third transistors (Q2a, Q8a) are a first type of transistor, and the second and forth transistors (Q4a, Q12a) are a second type of transistor;
wherein the bases of the first and second transistors (Q2a, Q4a) form the first non-inverting input (IN+A); and
wherein the emitters of the third and fourth transistors (Q8a, Q12a) form first the inverting input (IN−A).

17. The amplifier circuit of claim 16, wherein:

the first, third and fifth transistors (Q2a, Q8a, Q6a) are N-type transistors, and the second, forth transistors and sixth transistors (Q4a, Q12a, Q10a) are P-type transistors.

18. A method for amplifying common-mode (CM) signals using the generation of CM currents, comprising:

receiving an input signal (IN+A) at an input buffer (406a);
using the input buffer (406a) to produce a first current (½ IA), a second current (½ IA), a third current (−½ IA), and a fourth current (−½ IA);
using a first current mirror (410a) to provide the current proportional to the first current (½ IA) to a first high impedance node (414a);
using a second current mirror (412a) to provide the current proportional to the third current (−½ IA) to the first high impedance node (414a);
using a third current mirror (410b) to provide a current proportional to the second current (½ IA) to a second high impedance node (414b);
using a fourth current mirror (412b) to provide a current proportional to the fourth current (−½ IA) to the second high impedance node (414b);
using a first output buffer (408a) to buffer a signal at the first high impedance node (414a) and to produce a first output (OUTA) therefrom; and
using a second output buffer (408b) to buffer a signal at the second high impedance node (414b) and to produce a second output (OUTB) therefrom.

19. The method of claim 18, wherein the first current (½ IA), the second current (½ IA), the third current (−½ IA), and the fourth current (−½ IA) are proportional to a difference between the input signal and a fraction of its associated first output (OUTA).

Referenced Cited
U.S. Patent Documents
4904953 February 27, 1990 McCormack
5179355 January 12, 1993 Harvey
5187448 February 16, 1993 Brooks et al.
5266852 November 30, 1993 Shigenari et al.
5321370 June 14, 1994 Yukawa
5374897 December 20, 1994 Moravejii
5418495 May 23, 1995 Harvey
5420542 May 30, 1995 Harvey
5568089 October 22, 1996 Maru
5742154 April 21, 1998 Kolluri
5812026 September 22, 1998 Fairgrieve
6031424 February 29, 2000 Fairgrieve
6265941 July 24, 2001 Lopata
6362682 March 26, 2002 Shulman
6459338 October 1, 2002 Acosta et al.
6556081 April 29, 2003 Muza
6586997 July 1, 2003 D'Aquino
6636116 October 21, 2003 Cameron
6867649 March 15, 2005 Lehto
6888407 May 3, 2005 Ramazan et al.
6937100 August 30, 2005 Anderson
6998917 February 14, 2006 Kudo et al.
Patent History
Patent number: 7132859
Type: Grant
Filed: Mar 17, 2005
Date of Patent: Nov 7, 2006
Patent Publication Number: 20050207261
Assignee: Intersil Americas Inc. (Milpitas, CA)
Inventor: Jeffrey S. Lehto (San Jose, CA)
Primary Examiner: Timothy P. Callahan
Assistant Examiner: Hai L. Nguyen
Attorney: Fliesler Meyer LLP
Application Number: 11/082,423