Abstract: A network in a memory device for selecting a bit line during a data read or a data write. The network includes a first bit line in communication with a bitcell and a second bit line in communication with the bitcell. A charger is in communication with the first and second bit lines, and the charger is configured to charge the first bit line to a first charged level and the second bit line to a second charged level before a data read or a data write. A sensor is connected to the first and second bit lines. The bitcell drives one bit line up and the other bit line down during a data read. The sensor senses a difference between the first and second bit lines to select one of the first and second bit lines during a data read.

Abstract: The problems outlined above are in large part solved by an improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The front end includes a frequency synthesizer with an externally configurable charge pump on the tuner chip. The charge pump is coupled to a tank circuit having an adjustable resonance frequency. The resonance frequency can be adjusted over an entire octave by controlling the reverse bias voltage on a pair of varactors. A charge pump with a configurable gain is used to provide a control voltage to the tank circuit to provide a constant phase locked loop response over the frequency range of the tank circuit. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip is coupled to receive a receive signal and convert it to a baseband signal. The tuner chip includes an externally configurable charge pump, a tuning oscillator, and a downconverter.

Abstract: A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle.

Abstract: A semiconductor chip fabrication assembly and method including a semiconductor package having a packaging substrate and a semiconductor die. An active circuit surface of the semiconductor die is positioned adjacent to a contact surface of the packaging substrate such that a substantially thin gap is formed therebetween. A semi-rigid shroud device is provided which defines a vacuum chamber configured to extend around the gap to hermetically seal the gap within the vacuum chamber. A dispensing device is provided having an outlet end positioned proximate the gap in the vacuum chamber which is adapted to vacuum flow the bonding material between the electrical contacts in the gap, and between the active circuit surface and the contact surface. The absence of air and any other gases forms a substantially voidless underfill layer of bonding material in the gap.

Abstract: Semiconductor integrated circuits are electrically marked at final test time to form a permanent, visually and electrically readable record of the test results. The electrical record can provide a simple good/bad indication, i.e. indicate whether or not the device passed final test. This provides for more efficient handling of failed devices returned from the field, as the manufacturer can immediately determine whether the device in question passed final test before shipment--or inadvertently "escaped" from the manufacturer. The electrical marking technique, preferably using one or more fuses on board the device, can be used to record quiescent current test, speed sort test and various other final test results. These and other test results recorded on the chip are useful to quality and reliability studies, and in reducing the time and effort required to determine the failure mode of a returned device.

Abstract: An Integrated Circuit (IC) wafer test fixture includes a baseplate and a top plate. During testing, an IC wafer is positioned between the baseplate and top plate with annular rubber gaskets, forming sealed cavities above and below the IC wafer. A fluid pressure generator with a pressure gauge inserts a fluid under pressure into one of the cavities, causing the IC wafer to be subject to stress. The fluid distributes a uniform pressure load on the surface of the IC wafer. The pressure of the fluid may be gradually increased until a desired pressure is obtained or the wafer fails. The pressure at failure is recorded, and by calculation the failure stress of the IC wafer can be determined. A second embodiment of the test fixture includes a pressure vessel with a threaded sealed opening at the top and a stepped sealed opening at the bottom. The inner diameter of the insert is sized for an IC wafer. In use, the IC wafer is positioned on top of the insert, and the pressure vessel is sealed.

Abstract: In the manufacture of Printed Circuit (PC) boards, conductors are placed in a base layer of glass cloth. The conductors penetrate the thickness of the cloth and can be arranged to form a matrix or grid. The arrangement of cloth and conductors is then cured with resin with the wire lengths disposed within the cured board core. The wire lengths can be made flush with the board core surfaces and become the electrical conductors between circuitry on such surfaces. In one embodiment, the wire is removed leaving a finished hole ready for standard through-hole plating. These finished circuit boards can be stacked and laminated forming through, blind, or buried vias. One or more finished circuit boards with imbedded vias can be used as circuitry redistribution layers to avoid dense circuit patterns in applications such as in flip-chip mounting of integrated circuit chips. In another embodiment, the conductors are imbedded in the glass cloth with sufficient density to form a composite thick conductor.

Abstract: Format-independent electronic circuit descriptions are generated by providing incompatible sets of naming conventions, providing translation rules for generating circuit element names which satisfy all supported naming conventions, and modifying element names in accordance with the translation rules. Supported circuit descriptions may represent netlists defined by high-level design languages such as Verilog, EDIF, VHDL, and so forth, or may represent schematics or other symbolic representations. Any element associated with any input circuit representation may be tested or modified to ensure compatibility, such as the naming of logic cell types and instances, the naming of nets interconnecting logic cells, and the naming of input, output, and bidirectional ports. In a preferred embodiment, an element name to be resolved is inserted into a set of element names to determine whether the name is unique. If not, the proposed name is modified according to a set of modification rules until uniqueness is achieved.

Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

Abstract: A method for efficient, high quality rendering of a surface patch. The method tests a surface patch for flatness, and if the surface patch is not flat, the method divides the surface patch into a left surface patch and a right surface patch. Otherwise if the surface patch is flat, the method converts the surface patch into triangles. This method can be implemented to operate recursively, thereby ensuring that all portions of the patch are eventually converted into triangles when the portions become small enough to satisfy the flatness condition. A patch tests as flat only if all curves which form the patch do not deviate from straight lines by more than a predetermined tolerance. The division is efficiently performed by determining (i) left patch control points for a first portion of all curves along one axis of the surface patch, and (ii) right patch control points for a second portion of all curves along said axis of the surface patch.

Abstract: The present invention includes a modeling and testbench creation methodology which will allow a simulator to provide information regarding the state and direction of a bi-directional pad or pin. The present invention provides ATE tools all of the required data used to accurately and efficiently check for tester compatibility for which test patterns are extracted. In particular, the present invention includes a method of modeling a bi-directional I/O pad that includes the steps of providing a first signal in a first model; providing a second signal in a second model; and determining contention and direction of a resolved signal that is generated in response to at least one of the input and output signals. The first signal is a preferred output signal that is contained within an ASIC (first) model. The second signal is a preferred input signal that is contained within a testbench (second) model.

Abstract: A system arbitrator for a multi-function device is disclosed. The access arbitrator includes a bus access counter and comparator which are used to generate a bus request disable signal. The bus request disable signal for each function of the multi-function device is gated with the bus request signal for the function. As a function transfers data over the system bus, the access counter is incremented. When the access counter is incremented to a value which equals a predetermined maximum, the bus request disable signal becomes active and disables generation of bus requests for the function. In order to enable the bus signal generator for a function to begin generating bus requests, the access counters are reset when no bus request signals are being generated by any of the bus signal generators.

Abstract: The invention comprises an integrated circuit structure, and a process for making same, comprising a via/contact opening in a dielectric layer; a CVD layer of titanium nitride having a thickness of at least about 50 Angstroms, but not exceeding about 200 Angstroms, on the sidewall and bottom surfaces of the via/contact opening to provide adherence of the filler material to the underlying and sidewall surface of the opening; a CVD barrier layer of tungsten, having a thickness of about 50 Angstroms, but not exceeding about 300 Angstroms, formed over the titanium nitride layer; and the remainder of the via/contact opening filled with a highly conductive metal selected from the group consisting of copper, CVD aluminum, and force-filled aluminum.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which preserves frequency offset error tracking through a channel change. The demodulator/decoder receives the baseband signal and produces a compensation signal for canceling the frequency offset error. This is done using an element which generates a value indicative of the frequency offset error. Since the frequency offset error is independent of the selected channel, freezing the value indicative of the frequency offset error during a channel change enables a much faster acquisition of timing.

Abstract: In a redundant server network system, failover services for a failed server are provided by a survivor server belonging to a common failover group. At startup of a local server process running on the survivor server, a context is created for the local server and for each remote server belonging to the same failover group as the local server. At startup the context of the local server is also activated. The local server process is configured to operate on and make decisions based upon activated contexts. Each context includes server specific configuration and control information. When the survivor server must provide failover services for a failed server belonging to its same failover group, the context corresponding to the failed remote server is activated.

Abstract: The present invention presents a calibrator for a mobile station of a TDMA wireless communications system such that the calibrator calibrates a low-frequency clock to a high frequency clock locked to system timing. When the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and all clocks derived from it are turned off. Only the calibrated low-frequency clock remains operating to clock the sleep logic.

Abstract: This invention concerns a novel Viterbi decoding apparatus and method in which a survivor path unit (SPU) implements the traceback method with a RAM which stores path information in a manner which allows fast read access without requiring physical partitioning of the RAM. This results in an implementation that requires less chip area than conventional solutions.

Abstract: A device and method for characterizing signal skew between a first signal and a second signal. The device includes a delay chain and a first transition detector in communication with the delay chain. The first transition detector is configured for receiving the first signal and provides a pulse signal to the delay chain upon detecting a transition of the first signal. The device includes a second transition detector which is in communication with a latch and is configured for receiving the second signal. The second transition detector sets the latch upon detecting a transition of the second signal. At least one pass gate is connected to the delay chain and the latch. At least one timing latch is connected to the pass gate for receiving signal skew information between the first and second signals.

Abstract: A method and system for preventing smoke and fire damage in a clean room within which a tool including an electrically powered element is located. The method includes the step of providing the tool with a system including a fire proof housing, a sensor, an environmental sealing mechanism, an operator panel and a controller. The fire proof housing is secured over the tool and includes a door and at least one port to the tool. The sensor monitors an environmental condition within the housing and generates a sensor signal. The environmental sealing mechanism seals the at least one port and the door to the housing in response to the control signals to render the housing environmentally sealed. The operator panel includes visual indicators responsive to actuation signals. The controller is adapted to receive and process the sensor signals and to execute a shutdown control sequence during which the control signals and the actuation signals are generated.

Abstract: A novel device for pole splitting which can be employed in multistage amplifiers having a final stage and a prior stage. The device comprises a first capacitor connected between the output of the prior stage and the output of the final stage, a source follower, and a second capacitor connected between the output of the prior stage and the source follower. The source follower provides an offset voltage that reduces variation of the total capacitance of the first and second capacitors. In a preferred version of the present invention, the first and second capacitor each comprise a MOSFET transistor having a certain threshold voltage. The offset voltage is set to be at least the threshold voltage of the MOSFET transistors. In a preferred version, the source follower comprises a plurality of MOSFET transistors, which includes a MOSFET transistor having a gate connected to the first capacitor and a source connected to the second capacitor.