Abstract: A method and system for preventing smoke and fire damage in a clean room within which a tool including an electrically powered element is located. The method includes the step of providing the tool with a system including a fire proof housing, a sensor, an environmental sealing mechanism, an operator panel and a controller. The fire proof housing is secured over the tool and includes a door and at least one port to the tool. The sensor monitors an environmental condition within the housing and generates a sensor signal. The environmental sealing mechanism seals the at least one port and the door to the housing in response to the control signals to render the housing environmentally sealed. The operator panel includes visual indicators responsive to actuation signals. The controller is adapted to receive and process the sensor signals and to execute a shutdown control sequence during which the control signals and the actuation signals are generated.

Abstract: A preconditioning mechanism for preconditioning a polishing pad is described. The preconditioning mechanism includes an arm capable of being disposed over the polishing pad and a head section located on a distal end of the arm and rotatable about a central axis. Furthermore, the head section includes at least two heads oriented about the central axis and have surfaces for either conditioning or preconditioning the polishing pad, whereby rotation of the head section about the central axis by defined amounts presents at least two heads to the polishing pad so that different of the two heads can engage the polishing pad for conditioning or preconditioning depending upon how far rotation has proceeded.

Abstract: A gate array cell architecture is provided with routing tracks at variable track pitches, thereby increasing the density of the architecture. Orientation of the devices in the gate cells perpendicularly to the routing tracks in the second metallization layer provides an increased porosity in this layer. The orientation allows an N channel device to be made smaller than a P channel device within a gate cell, to provide balanced devices. The perpendicular orientation also provides more contact points for source or drain. When the mulitple contacts are used to connect the device to a power source, the multiple contacts reduce the effective resistance and increase the reliability of the devices.

Abstract: A die is unpackaged from a Chip on Tape by grinding off molding compound from an upper surface of the COT until the COT's leads are evenly exposed across the upper surface, selectively etching out the leads using the remaining molding compound as a mask, removing an underlying layer of gold plating, and then removing the remaining molding compound. The unpacked die can then be reframed with new leads and molding compound for failure analysis and electrical failure verification.

Abstract: An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.

Abstract: A receiver is described for recovering digital data from a transmitted balanced signal where the balanced signal includes a first plurality of pulses, each pulse having a first pulse width. The receiver includes an input circuit, a buffer circuit, and a calibration circuit. The input circuit receives the transmitted signal and includes a first differential amplifier for amplifying a first signal, a second differential amplifier for amplifying a second signal, and a converter for receiving the amplified first signal and amplified second signal and then generating a third signal. The first and second signals are included within the transmitted signal. The buffer circuit receives and buffers the third signal, and outputs a fourth signal including a second plurality of pulses which have a second plurality of pulse widths. The calibration circuit receives the fourth signal.

Abstract: A low threshold voltage MOS device on a semiconductor substrate is disclosed. The substrate has an upper surface, and a first well region is disposed in said semiconductor substrate extending downwardly from the semiconductor substrate upper surface. The first well region includes a dopant of a first conductivity type having a first average dopant concentration. Source and drain regions of a second conductivity type are laterally spaced from each other and are disposed in the first well region, the source and drain regions extending downwardly from the semiconductor substrate upper surface a predetermined distance. A channel region comprising the first well region of the first conductivity type is disposed between the source and drain regions. The channel region also extends at least the predetermined distance below the semiconductor substrate upper surface.

Abstract: A process and resulting product are disclosed for an integrated circuit structure including two or more metal wiring levels interconnected by metal-filled vias. A first insulation layer, such as an oxide layer, is formed over a first metal wiring level on an integrated circuit structure. A via mask layer, such as a nitride mask layer, is then formed over the insulation layer with openings formed in the via mask layer in registry with portions of the underlying metal wiring to which it is desired to make electrical contact by the formation of vias through the first insulation layer. A second insulation layer, which may comprise a second oxide layer, is then formed over the mask layer. A reverse second metal wiring level mask, such as a photoresist mask or another nitride mask, is then formed over the second insulation layer to define the second metal wiring. The second insulation layer is then anisotropically etched with an etchant which is selective to the second level metal wiring mask and the via mask, i.e.

Abstract: A test method for a memory device wherein failures that may only occur under specified worst-case conditions are converted to hard functional failures. These locations are subsequently detected and remapped by built-in self test (BIST) and built-in self-repair (BISR) circuitry. First, a test suite is performed on a memory array which includes redundant row and column locations. Typically, this test suite is performed under conditions which are most likely to induce failure. Row and column locations that are determined to be malfunctioning are scanned out of the memory device, along with the number of available redundant rows and columns. If there are sufficient redundant locations, the failing rows and columns are permanently disabled by blowing each of the corresponding fuse links. When power is subsequently applied to the memory device, BIST will detect rows and columns, including those permanently disabled, with hard functional failures. Accesses to these locations may then be redirected by BISR circuitry.

Abstract: A computer system and method for generating a hardware description language source code file with embedded microcode segments for describing control logic of a complex digital system. A macro file is defined, comprising source code written in the hardware description language and a macro name associated with a segment of the source microcode in the macro file. A skeleton file is defined, comprising source code written in the hardware description language and including a reference to the macro name. The skeleton file is combined with the segment of the source microcode from the macro file at the reference to the macro name using a preprocessor to form a final source code file. Preferably, each microcode segment is encapsulated between a pair of comment statements expressed in the hardware description language.

Abstract: An instruction (also called a "bit reversal instruction") for reversing the order of bits in an input signal is implemented by reusing one or more components in a datapath normally found in a processor. Specifically, a bit reversal instruction is implemented by reuse of a shifter unit normally used in a datapath to shift bits of an input signal. The shifter unit includes three stages: a first stage formed by a number of input multiplexers, a second stage formed by, for example, a left shifter, and a third stage formed by a number of output multiplexers. When using a left shifter to implement the bit reversal instruction, the input multiplexers are not used. Instead, the left shifter is used to shift bits of the input signal left by a number that is inverse of the number of bits to be reversed. Thereafter, the output multiplexers reverse the order of bits generated by the left shifter, thereby completing the bit reversal instruction.

Abstract: A phase locked loop, which does not require a local reference clock to obtain a frequency lock. The circuit includes a frequency locked loop and a phase locked loop in which the frequency locked loop does not require a local reference clock. The frequency locked loop includes a transition counter having an input for data with an output connected to a charge pump. This charge pump is connected to a loop filter, which in turn is connected to a voltage controlled oscillator. The output of the voltage controlled oscillator is connected to a second input in the transition counter. The phase locked loop includes a phase detector with an input for data. The output of this phase detector is connected to a second charge pump, which has it output connected to the loop filter. The output of the voltage controlled oscillator also is connected to the input of the phase detector.

Abstract: A Viterbi calculator performs additions in parallel with comparison to compute the result of a single Viterbi equation in a single clock cycle. Therefore, the results of a butterfly operation involving two Viterbi equations can be computed in a single clock cycle by use of two Viterbi calculators. Alternatively, the butterfly operation can be implemented by a single Viterbi calculator used in a pipelined manner, although the throughput is at the rate of every two clock cycles. When a single Viterbi calculator is used in the pipelined manner, two multiplexers are used to alternately swap the constant values being supplied to the Viterbi calculator. The pipelined use of a single Viterbi calculator requires less space on an integrated circuit die than the parallel use of two Viterbi calculators, and is useful in applications where the variable data is available every two clock cycles (e.g. due to latency in accessing memory).

Abstract: An automated endpoint detection process includes obtaining a baseline graph of reflected radiation signal versus time of radiation exposure for a standard integrated circuit substrate surface that is substantially free of residual metal, directing radiation generated from a radiation source through a radiation transparent region of a polishing pad such that radiation is incident on at least a portion of a surface of the integrated circuit substrate, detecting a reflected radiation signal from the integrated circuit substrate surface through the radiation transparent region of the polishing pad, comparing an area under a graph of the reflected radiation signal versus time of radiation exposure obtained for the integrated circuit surface to the baseline graph of the standard integrated circuit substrate surface and thereby determining whether residual metal is present on the surface of the integrated circuit substrate and signaling the chemical-mechanical polishing assembly to stop polishing after polishing for

Abstract: A novel method for PN sequence hopping where a PN sequence generator has been disabled for a predetermined time before a future time slot where the PN sequence generator will be enabled. The method comprises the steps of writing a base state into storage for a first hop only, calculating from the base state a new state advancing a PN sequence to the beginning of the future time slot, loading the new state into the PN sequence generator, and enabling the PN sequence generator. For subsequent hops, the base state is the new state calculated in the previous hop. In a preferred version, the step of calculating a new state comprises multiplying the base state by a Galois Field polynomial; a serial Galois Field multiplier can be used to perform this multiplication. A system embodying the present invention comprises a PN sequence generator, a control processor, and a storage device.

Abstract: Microprocessor main programs and their interrupt handling routines are written in a high level programming language such as C. Each is compiled separately, and each is compiled invoking a compiler option which commands the compiler to not use a given set of registers in the compiled code. Post-processing is then performed on the compiled interrupt code to replace accesses to a first set of registers with accesses to the given set of registers. The result is that while both the main program and the interrupt handler were written in C, the compiled code for each employs different registers. This allows context switching from the main program to the interrupt handler and back again with almost none of the overhead traditionally associated with context switching register save and restore operations during exception handling.

Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating.

Abstract: A reconfigurable built-in self test circuit for enabling the debugging of an embedded device. In one embodiment, the write data path from the built-in self test module to the embedded device includes a multiplexer which is controlled by a debug signal. When the debug signal is de-asserted, the multiplexer forwards the write data from the built-in self test module to the embedded device, thereby allowing the self test to proceed in the hard wired manner. When the debug signal is asserted, the multiplexer forwards external data from the user to the embedded device, thereby allowing the user to execute customized tests on the embedded device. A second multiplexer is similarly placed in the expected data path from the built-in self test module to the comparator to allow the user to provide external data for comparison with output data from the embedded device when the debug signal is asserted.

Abstract: A method and apparatus for providing automatic termination of cables coupled to an adapter card is described. The presence or absence of devices attached to such cables are sensed. A terminator circuit is selectively activated to provide termination for the cables depending on the configuration of devices attached to the adapter card. In one embodiment, a plurality of dissimilar types of devices having different data widths are attached to a common adapter card via a plurality of cables. The cables provide for interconnection of devices to the adapter card via a bus protocol. The signals to/from the cables are sourced/sinked from a controller chip. A terminator circuit in close proximity to the controller chip is selectively activated to provide termination for the host side of the bus, depending on the types of devices attached to the bus.

Abstract: A bus bridge circuit having at least one register to store address ranges to enable or disable prefetch in upstream memory read transactions or upstream write transaction buffering/posting data to specific devices. The use of address ranges allows the present invention to provide selectable control of prefetch for upstream memory read transaction flow. This feature allows the continued use of read prefetch for targets that allow upstream read prefetch while disabling upstream read prefetch for targets that do not allow upstream read prefetch. Additionally, the use of the address range allows upstream memory write transaction flow without utilizing data buffering or posting for specific targets. This feature provides immediate delivery of upstream data to selected targets by selectively disabling buffering/posting of upstream memory write commands as performed by a FIFO buffer.