Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating.

Abstract: A multithreaded wavefront routing system for simultaneously planning routes for wiring a semiconductor chip surface. The surface has a plurality of grids located thereon, and routes are planned according to a predetermined netlist. The system steps across the surface from a first location to a second location in a wave-type pattern. The system sequentially steps through the grid arrangement on the chip surface and plans routing one grid at a time using a plurality of threaded processors. The system recognizes pins as it steps through grids and determines a plan for the current grid by evaluating current wire position, target pin location, and any currently planned routes, designating reserved locations wherein the route may be planned subsequent to the current grid, and establishing a wire direction for each wire traversing the current grid.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected.

Abstract: An automatic baud rate detector circuit includes a serial input, a counter, a register, a comparator and a state machine circuit. The serial input receives a serial data stream having a bit defined by a first transition from a first logic state to a second logic state and next subsequent second transition from the second logic state to the first logic state. A counter increments a sample count in response to a clock signal when a count enable signal supplied to the counter is active. A register coupled to the counter stores the sample count as a minimum count when a load control signal supplied to the counter is active. The comparator is coupled to the counter and the register and generates a compare signal which indicates whether the sample count is less than the minimum count. The state machine circuit is coupled to the serial input for receiving the serial data stream and supplies the count enable signal to the counter and the load enable signal to the register.

Abstract: A bitstream management system and method which provides an infrastructure to enable comprehensive testing of devices that implement multiple syntax rule sets. In this system and method, modules for the individual syntax rule sets are implemented using profiles (concise representations of data streams). The modules each have a profile generator which determines a permutation of selected values for a set of syntax variables and translates that permutation into a profile. The modules also each have a data stream generator which converts the profiles into the data streams they represent. The use of profiles provides an advantageous method for maintaining the modularity of the syntax modules when integrating them together to provide a system for generating data streams which must comply with multiple syntax rule sets.

Abstract: Provided is a method and composition for reducing the rate of, and rendering more uniform the oxidation of alignment mark trench side walls by CMP slurry accumulating in an alignment mark trench during CMP processing. In a preferred embodiment, a nucleation layer of tungsten having an equiaxed grain structure with fine grain size and conformity is deposited over a conventionally applied bulk tungsten layer prior to commencing CMP operations. The fine grain size and equiaxed grain structure of this nucleation layer make it more resistant and more uniform in response to slurry attack. As a result, the tungsten trench profile remains a consistent and reliable alignment mark.

Abstract: A virtual monitor controller includes a data storage device coupled to receive and output data; an instruction storage device coupled to receive and output instructions; a status storage device coupled to receive and output status data; and a mode storage device coupled to receive and output mode data. The virtual monitor controller is included in a debugger/monitor controller. A debugger/monitor system comprises a host system; the debugger/monitor controller; and a digital processor. Preferably, the controller is coupled between the processor and IC logic. A method of operating a virtual monitor comprises the steps of intercepting an instruction fetch from a microprocessor; downloading instructions from a host computer; and operating the microprocessor with the instructions. Preferably, the instructions are sequentially downloaded.

Abstract: A technique for designing circuits with arithmetic or logic functions on integrated circuit devices. The circuit has a primary chain of serially connected logic blocks and secondary chains of serially connected logic blocks. The output node of the last logic block of each secondary chain is connected to an input node of a logic block in the primary chain. Depending upon the desired function, the logic blocks can be logic gates or more complex logic blocks. Zero detect and compare circuits can be designed from this basic arrangement. Connected with input logic, output logic and merge logic, other circuits, including incrementors, decrementors, priority logic, adders and ALUs, are possible. The resulting circuit occupies far less space on an integrated circuit than a fully parallel, lookahead circuit, yet operating speeds are comparable.

Abstract: A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Abstract: A camera comprising various arrangements for employing optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements. and methods of making same are discussed.

Abstract: A circuit and method for generating a generally logarithmic transfer function based upon switching signals. The circuit includes a plurality of transistors and a switch operatively connected to each transistor in the programmable set. A line is in communication with each switch for carrying switching signals thereto thereby selecting which of the transistors will contribute to the generally logarithmic function. Preferably, the circuit is a portion of a programmable gain amplifier, and a digital code controls the gain. The gain can be generally logarithmic as a result of which transistors which are selected to contribute to the generally logarithmic transfer function. For example, there may be a plurality of sets of transistors where the values of the transistors in each set are such that when all the transistors of the set are selected to contribute to the generally logarithmic gain, the set of transistors provides a gain having a value approaching m.

Abstract: An electrode assembly for a plasma reactor used in connection with fabrication or manufacture of semiconductor devices. The electrode assembly includes an anode having, a top side that includes a pedestal adapted to support a wafer and defines an annular void that preferably surrounds the pedestal and extends to an outer periphery of the top side. The electrode assembly also includes a ring removably received within the annular void so that the ring extends from the pedestal and covers substantially the entire portion of the top side of the anode save the pedestal. The thickness of the ring is slightly less than the height of the pedestal so that the top surface of the ring is located below the top surface of the pedestal. When the wafer is supported by the pedestal during fabrication of a semiconductor device, the wafer extends beyond the circumference of the pedestal, and a gap is defined between the wafer and the removable ring. The removable ring can be quickly and easily removed and replaced.

Abstract: A highly integrated, single chip computer system having not only a central-processing unit (CPU) but also specialized coprocessors. The specialized coprocessors, for example, enable the single chip computer system to be reasonably sized, yet perform high quality video (e.g., MPEG-2) and graphics operations (e.g., three-dimensional graphics). The single chip computer system offers improved performance of video and graphics operations, resource scheduling and security. The improved security offered by the single chip computer system enables program code or data stored external to the single chip computer system to be encrypted so as to hinder unauthorized access, while internal to the single chip computer system the program code or data is decrypted. The single chip computer system is particularly suitable for video game consoles having high quality graphics and/or video, digital video disk (DVD) players, and set-top boxes.

Abstract: An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.

Abstract: An electronic semiconductor device package, the package comprising: a substrate having traces; a die attached to the substrate; first level interconnects of the die to the traces of the substrate; and a stiffener attached to the substrate, wherein the stiffener comprises at least one slot. A system for attaching a heat sink to an electronic semiconductor device package, the system comprising: a stiffener of the electronic package which is attachable to the electronic package; a clip which secures the heat sink to the stiffener; and at least one slot in the stiffener which receives the clip. A method of detachably attaching a heat sink to an electronic semiconductor device package, the method comprising: attaching a stiffener to the package, wherein the stiffener comprises at least one slot; positioning a heat sink adjacent the stiffener; and engaging a clip with the slot and the heat sink, wherein the heat sink is secured to the stiffener by the clip.

Abstract: A DRAM memory array is organized hierarchically into groups of DRAM segments, bit blocks within segments, and memory cells within bit blocks, arranged in rows and columns. A control and logic circuit extends along the rows and columns and segment buses extend from the control and logic circuit to the DRAM segments. Partial decoding of the address and control signals occurs in the control and logic circuit and the partially decoded control and address signals are supplied on the segment buses. Adaptable memory operations are controlled in the control and logic circuit, such as redundant element substitution, data block addressing, multiplexing of the data bit width signals available at the DRAM segments to the width required by a system bus. This flexibility allows various physical organizations of the DRAM array.

Abstract: Method and apparatus for transferring data on a voltage biased data line are disclosed. In one embodiment, there is provided a bus interface for controlling a differential bus having a differential data line that includes a first bus line and a second bus line. The bus interface includes a bus controller circuit, an impedance network, and a controllable biasing circuit. The bus controller circuit is coupled to the differential bus and is configured to (i) control transfer of data across the differential bus, and (ii) generate a biasing control signal prior to data transfer on the differential data line. The impedance network is coupled to the first bus line and the second bus line and is configured to substantially match a characteristic impedance of the differential data line.

Abstract: Methods and associated apparatus within a RAID subsystem having redundant controllers define a private LUN as a data storage area known and accessible to all controllers in the system and used by them for diagnostic purposes. The methods involve sending a diagnostic write command to a first controller with instructions for it to write test data to the private LUN. This first controller writes this test data to the private LUN. A second controller, in response to another diagnostic command, then reads this test data from the private LUN and compares it to expected values provided in the diagnostic command. Using the results, it can then be determined which controller, if any, failed. If the first controller fails, then the second controller takes over ownership of portions of the data storage area assigned to the first controller. The private LUN is preferably striped across all channels used by the controllers to communicate to commonly attached disk drives.

Abstract: The present invention provides for novel off-axis illuminator lens masks for semiconductor photolithographic projection systems. The masks are rotationally symmetric along axes 60.degree. or 120.degree. apart. Such masks can increase the contrast 30.degree. and 60.degree. with respect to the X and Y axes of an integrated circuit in a semiconductor wafer for the optimum printing of conducting lines along these directions.