Abstract: The present invention provides for novel off-axis illuminator lens masks for semiconductor photolithographic projection systems. The masks are rotationally symmetric along axes 60.degree. or 120.degree. apart. Such masks can increase the contrast 30.degree. and 60.degree. with respect to the X and Y axes of an integrated circuit in a semiconductor wafer for the optimum printing of conducting lines along these directions.

Abstract: A method for comparing intermediate test files having different file formats used to test integrated circuitry is provided. The method initially receives intermediate test files from an ATPG tool or a manually run simulation. The ATPG tool or manually run simulation provides data in a .wgl format for testing, and is a non-simulatable format, and the ATPG tool also provides a second intermediate file comprising a file or files in a simulatable format. All files contain event data used for testing. The intermediate test files are converted to files having a common format. The invention then compares the converted files to determine mismatches between the converted files. This comparison comprises evaluating the common format files and generating a pass/fail flag based on the results of the evaluation. Mismatches between the common format are corrected if the flag indicates that the files are not identical.

Abstract: A ball grid array package (BGA) according to the present invention has an interposer between a bond pad on the lower surface of the substrate and the solder ball. The interposer has a conductive portion in contact with the bond pad surrounded by a nonconductive or insulating portion. The conductive portion in contact with the bond pad is sufficiently constrained from widening during a subsequent reflow process by the presence of the nonconductive or insulating portion. The contact with the bond pad is sufficiently small to allow traces to pass near the bond pad substantially directly en route to another bond pad. The nonconductive portion also prevents subsequently-applied encapsulant from coming in contact with and contaminating the bond pad. The elevated surface of the interposer, i.e. the surface of the interposer furthest from the bond pad, supports the solder ball, and is sufficiently wide to support the solder ball without allowing the solder ball to come in contact with the traces.

Abstract: A PBGA package includes PBGA member, a stiffener ring, and a stiffener fixture which includes a retaining recess having a floor for receiving the stiffener ring and includes a ledge positioned above the recess floor for receiving the PBGA member. An adhesive layer is applied to the stiffener ring, which is adhered to the PBGA member. The stiffener ring and PBGA member are essentially coplanar to less than 8 mils. A top plate is placed on top of the PBGA member and the ring and member are secured together tightly.

Abstract: An apparatus and method for packaging an integrated circuit having a semiconductor die with electronic circuitry disposed thereon includes lead frames for mounting thereon solder balls of a ball grid array packaging structure. In one embodiment, the semiconductor die is coupled to conductors of the lead frame via gold wires attached to both the semiconductor die and the lead frame. The lead frame is encapsulated in plastic with apertures disposed therein for exposing upper and lower portions of conductors of the lead frame. The apertures are filled with solder balls to contact both the upper and lower portions of the lead frame conductors. Solder balls on the top of one integrated circuit package may be connected to mating solder balls on the bottom of another integrated circuit package, and so on, thereby achieving multiple stacking of integrated circuit packages.

Abstract: A method for simulating an integrated circuit design that automatically generates an interface between a test bench and a device design for simulation. The method determines that the signal format and timing information of the test bench conforms to the constraints of some target ATE. If the information conforms, an array of buffers is created to provide the interface. Each of the buffers are defined according to the signal timing information. The interface is then incorporated into a test bench stimuli generator and the design is simulated. In this manner, the method allows for the generation of a simulation that can be then reproduced on any target ATE.

Abstract: The present invention includes a Chien search device that implements an error-locator polynomial divided by a factor. The device includes first and second devices to generate .alpha..sup.i and .alpha..sup.-i, respectively. The device also includes a root determination block coupled to receive .alpha..sup.i and .alpha..sup.-i to provide a signal responsive to .alpha..sup.-i. In particular, the signal represents that .alpha..sup.-i is a root of the error-locator polynomial. The root determination block includes multiple root determination circuits to find the roots of the error-locator polynomial for each data interleave.

Abstract: A semiconductor device and fabrication method are presented which advantageously combine TAB and wire bonding techniques to increase integrated circuit I/O pad density. The semiconductor device includes an integrated circuit, a substrate, and a carrier film (i.e., a TAB tape). The integrated circuit has a set of input/output (I/O) pads arranged upon an upper surface. The substrate has a die cavity within an upper surface and a set of bond traces arranged about the die cavity. An underside surface of the integrated circuit is attached to the substrate within the die cavity. The carrier film is positioned over the upper surface of the substrate such that the upper surface of the integrated circuit is exposed through a die aperture and portions of the members of the set of bond traces are exposed through corresponding members of a set of bond trace apertures.

Abstract: A method and apparatus for converting a layout design for the metallization layer integrated circuit pattern to a reticle design having corrections for depth of focus problems. The apparatus includes a design rule checker which is configured to identify locations of the layout design which are expected to produce narrowed regions of the image caused by depth of focus variations at intersections between defined line features of the layout design and the elevated portions of the topographical variations. A depth of focus correction unit is included which is adapted to modify the layout design for the metallization integrated circuit pattern at the locations by increasing the line width of the defined line features from the integrated circuit pattern to correct for these depth of focus problems.

Abstract: A shielding conductor is spaced from a matrix of memory cells in a dynamic random access memory (DRAM) to shield the memory cells from noise signals, such as the noise created by components of a system level integrated circuit (SLIC). The shielding conductor is connected to one of a reference or potential source, preferably external to the DRAM segment. The shielding conductor distributes the effect of noise and maintains a uniform reference potential with respect to the DRAM components with which it overlays or connects. The shielding conductor comprises a plurality of connected intersecting conductors which form a mesh which overlays substantially the entire matrix. The mesh is connected to components, such as an isolating well or a capacitor reference potential conductor, at a plurality of spaced-apart locations over the entire matrix. The shielding conductor may also be a single integral conductor which overlays the entire matrix, including the bit and word lines.

Abstract: The invention provides a method and apparatus for increasing the efficiency of data transfer between a host computer and a disk array in a RAID system. The invention operates by splitting up large I/O requests from the computer into smaller, more manageable pieces and processing the pieces as though they were individual I/O requests. In one embodiment, the invention keeps only a limited number of these smaller individual I/O requests "active" at any particular time so that a single large I/O request cannot preclude other I/O requests from making progress in the controller. Both the size of the smaller I/O request pieces and the limited number of these pieces which will be "active" at any one time may be tunable parameters. The invention improves the efficiency of data transfer between the host computer and the array of disk drives by providing for increased overlap of activity in the controller. This increased overlap of activity results in increased controller throughput.

Abstract: A data frame synchronizer identifies frame boundaries in a serial data stream formed of a set of multi-bit frames. Selected frames in the set have a frame boundary bit at a specified location within the frame, and the frame boundary bits together form a predetermined pattern. The frame synchronizer includes a memory array having a memory data input, a memory data output and a plurality of rows and columns for storing the serial data stream. A memory control circuit is coupled to the memory array for writing successive bits of the serial data stream into the memory array through the memory data input in a sequence such that all of the frame boundary bits align in one of the rows. As each bit is being written into the memory array, the memory control circuit reads the corresponding row through the data output. A pattern detector is coupled to the memory data output for comparing the row with a predetermined pattern.

Abstract: A semiconductor device and fabrication method are presented which employ a thermally conductive substrate having an outer layer of palladium. The substrate may be made of, for example, a metal such as copper. The substrate does not itself include layers of signal traces or bonding pads which function as device terminals, but provides a stiff backing for support of a flexible circuit which includes signal traces and bonding pads. An adhesive layer bonds the flexible circuit to the substrate. The outer layer of palladium has a desired surface roughness and chemical properties which improve the adhesion of the adhesive layer to the substrate. The substrate has opposed, substantially planar upper and underside surfaces. In one embodiment, the underside surface of the substrate has a die cavity, and the flexible circuit includes a set of conductors bonded to one side of a sheet of dielectric material (e.g., polyimide film).

Abstract: A system for providing an optimal cluster of cells on the surface of a semiconductor chip is provided herein. The system collects a predetermined quantity of cells, this predetermined quantity containing a center cell, and all cells are assigned a distance value from the center cell. A coordinate is assigned to each cell based on its associated distance value, and new cell positions are calculated based on related cell positions and weights associated with each cell.

Abstract: A memory device including a plurality of memory cells, a plurality of bit lines, a plurality of bit line sense amplifiers, a plurality of column port gates, and a column decoder connected to a multiple of five column port gates. Each of the bit line sense amplifiers is connected to at least one of the bit lines and to at least one of the memory cells. Each of the column port gates is connected to at least one of the bit line sense amplifiers. The column decoder provides signals to the column port gates to which it is connected to select corresponding bit lines connected to the column port gates.

Abstract: A system and method for estimating motion vectors between frames of a video sequence which operates with reduced memory loading latency according to the present embodiment. The motion estimation system includes a motion port pixel processing array according to the present embodiment. The processing array includes a reference block memory array for storing a reference block and a candidate block memory array for storing a candidate block. According to the present embodiment, each of the reference block memory array and candidate block memory array are configured with dual ports to a reference block memory and a search window memory. Each of the reference block memory array and candidate block memory array are further configured to allow dual port loading during the entire initialization sequence, when one or more of either a reference block or candidate block is being loaded into the respective memory array.

Abstract: A semiconductor package having positioned therein a protection layer which protects the integrated circuit chip from electrostatic discharge (ESD) damage. The protection layer is made of a material that has at steady state a high electrical resistance, but when a high ESD potential is applied to it, it becomes highly conductive. A preferred material is SurgX.TM., which is a polymer. The layer is positioned to shunt the potential away from the chip, and can be positioned operatively between a signal lead and a power plane or between different signal leads. That is, the protection layer can be sandwiched between the lead and the conductive member, or the lead can be within the layer. Another preferred construction incorporates the protection material in a tape construction as a thin layer sandwiched between and bonded to a layer of leads and a ground plane.

Abstract: A single chip integrated remote access processor circuit has a plurality of communication interface units, including a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit. A data routing control circuit is coupled to the plurality of communication interface units for controlling data transfer between the interface units.

Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

Abstract: A method and apparatus for efficiently posting entries to a queue within the data processing system. Entries are posted by first processor with the entries being handled by second processor in the data processing system. The interrupt state associated with the queue is checked by the first processor. If the interrupt state is clear, then the entry is posted to the queue. This interrupt state is cleared only when all entries have been cleared from the queue by the second processor. In this manner, an efficient posting of entries to the queue may be accomplished.