Abstract: A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

Abstract: A DRAM cell capacitor is described. Capacitor formation and cell isolation methods are integrated by using existing isolation trench sidewalls to form DRAM capacitors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor.

Abstract: An apparatus generally comprising an input circuit, a storage circuit and an output circuit is disclosed. The input circuit may be configured to generate a first intermediate signal from a plurality of input video signals. The storage circuit may be configured to (i) organize the first intermediate signal into a plurality of sequences each related to one of the input video signals and (ii) generate a second intermediate signal from the sequences. The output circuit may be configured to generate an output video signal by compressing the second intermediate signal.

Abstract: Disclosed is a method for translating a SPICE format circuit description to Verilog format and design method employing Verilog to SPICE and SPICE to Verilog translation, allowing simulation in Verilog or SPICE formats and allowing verification of Verilog to SPICE translation. SPICE to Verilog translation may employ identification of SPICE sub circuits, circuit elements, input signals, and output signals; and translation of these to Verilog format wherein signal names and design hierarchy can be maintained. Circuit element instance names may be translated to Verilog names associated with SPICE instance names. Identification and translated may employ lookup tables, rule sets, specialized filed delimiters, naming conventions, or combinations thereof. An intermediate file of input and output signals may be created. SPICE node names may be converted to Verilog wire definitions.

Abstract: Disclosed is an improved hard macro design for use in an ASIC, which avoids undesirable buildup of electrostatic charge on a gate of an I/O transistor of the hard macro. The hard macro includes a port level metallic conductor of an I/O port positioned at a low level metalization layer and an electrical connection between the port level metallic conductor and a gate conductor of the I/O transistor. The electrical connection includes a first conducting section extending from the gate conductor to a top level metallic conductor at a highest level metalization layer and a second conducting section extending from the top level metallic conductor layer to the port level conductor. Antenna rule violations at the I/O port of the hard macro are eliminated due to the electrical connection between the top level metallic conductor and a diffusion region.

Abstract: A package substrate is contemplated herein for reducing cross-talk for noise-sensitive signals. The package substrate includes noise-sensitive conductors adapted to receive the noise-sensitive signals. In one embodiment, the cross-sectional width of the noise-sensitive conductors is increased to reduce certain parasitic effects such as resistance and/or inductance. The package substrate also includes guard conductors which are arranged co-planar with and substantially parallel to the noise-sensitive conductors. A plurality of vias spaced equidistant from one another extends from a ground conductor to the guard conductors, providing a substantially uniform voltage across the guard conductors. The overall effect will reduce the inductive and capacitive cross-talk from neighboring signals and increase the signal integrity of noise-sensitive signals.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.

Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.

Abstract: A mechanism if provided for testing newly-manufactured integrated circuits at the wafer stage. Built-in self-test circuitry is used to test each of the die on a wafer in parallel. Then, when a defect is detected, the die marks itself (e.g., by physically destroying a portion of itself through burnout). The present mechanism eliminates the inefficiencies of serial testing of die and of mechanical latency as each die is positioned for testing.

Abstract: A method of applying a layer of a flowable material to a substrate. The substrate is received with a rotatable chuck, and an amount of the flowable material is dispensed on to the substrate. The substrate is spun on the rotatable chuck, thereby spreading the flowable material across the substrate and conveying a surplus amount of the flowable material away from the substrate. An exhaust stream is created with a vacuum source. At least a portion of the surplus amount of the flowable material conveyed away from the substrate is entrained into the exhaust stream, which exhaust stream is conveyed into an exhaust system. A pressure drop is created in the exhaust stream across a vane anemometer within the exhaust system. The blow back of the entrained portion of the surplus amount of the flowable material from a downstream position in the exhaust system to the substrate is thereby reduced.

Abstract: The amount of data transmitted in a primary data channel is increased by modulating a reference clock signal of the primary data channel with secondary data to form a separate secondary data channel. Primary data is formed into a primary data signal using the modulated reference clock signal, and a transmitter transmits the primary data signal to a receiver. The receiver recovers the primary data and modulated reference clock signal from the primary data signal, and then recovers the secondary data from the recovered modulated reference clock signal.

Abstract: A bridge for connecting a DSP to an ASIC on-chip bus as a slave. The bridge couples signals between a DSP internal memory direct memory interface and an on-chip bus such as the AMBA AHB. The bridge includes a generic slave module which provides direct connections to the on-chip bus in the on-chip bus protocol. It also includes a slave engine connected to the DSP memory interface to control read and write transactions with the memory. The generic slave and the slave engine are coupled by a pulse grower and pulse shaver to allow the engine to operate at DSP clock frequency while the generic slave operates at the usually slower on-chip bus frequency. The bridge allows masters in the ASIC to perform read and write transactions with the DSP internal memory.

Abstract: A method of detecting spatially correlated variations that may be used for detecting statistical outliers in a production lot of integrated circuits to increase the average service life of the production lot includes measuring a selected parameter of each of a plurality of electronic circuits replicated on a common surface; calculating a difference between a value of the selected parameter at a target location and a value of the selected parameter an identical relative location with respect to the target location for each of the plurality of electronic circuits to generate a distribution of differences; calculating an absolute value of the distribution of differences; and calculating an average of the absolute value of the distribution of differences to generate a representative value for the residual for the identical relative location.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of intermediate signals from a data signal. Each of the intermediate signals may be switchable between (i) a common delay and (ii) one of a plurality of different staggered delays determined by a stagger signal. The a second circuit may be configured to generate a plurality of first drive signals by gating the intermediate signals with a plurality of enable signals. The a third circuit may be configured to generate a plurality of first output signals at a transmit interface of a chip by buffering the first drive signals.

Abstract: The present invention is directed to a system and method of providing an embedded input/output interface dynamic load balancing. A method for providing a load balancing function between a host and a target in a network environment by an input/output interface may include providing a logical identifier table by an input/output interface, the logical identifier table including at least one logical identifier, the logical identifier suitable for referencing at least one physical address identifier of a target. Communications are managed between the host and the target by the input/output interface. The communications occurring over at least one of a first route and a second route of at least two routes communicatively coupling the input/output interface to the target are managed so that the host transfers data by balancing data transferred utilizing the second route and the third route of the at least two routes.

Abstract: A system for controlling arbitration that may be used for a bus. The system generally comprises a bus, at least one master, and a first circuit coupled between the bus an the at least one master. The at least one master may be configured to present at least one transfer signal. The first circuit may be configured to (i) grant a bus mastership to a first master of the at least one master, (ii) present a first transfer signal of the at least one transfer signal to the bus in response to granting the bus mastership to the first master, (iii) remove the bus mastership from all masters of the at least one master, and (iv) present an idle transfer signal to the bus in response to removing the bus mastership from all masters.

Abstract: A method of power sequence protection for a level shifter is disclosed that includes the steps of placing the level shifter in a pre-selected state if an input voltage supply is not powered on when an output voltage supply is powered on and releasing the level shifter from the pre-selected state to follow transitions of an input signal when the input voltage supply is powered on.

Abstract: Different dynamic range control values are applied to the 2-channel and m-channel outputs without repeating the inverse transform or the windowing of the audio samples. First, m-channel dynamic range control values are applied to audio samples in the frequency domain (“frequency samples” or “frequency coefficients”). The frequency samples are then inverse transformed to generate audio samples in the time domain (“time samples”) and windowed to generate windowed time samples. The windowed time samples are saved and the 2-channel dynamic range control values are applied to the windowed time samples. 2-channel dynamic range control values include 2-channel scale factors that, when multiplied with groups of the windowed time samples, at least partially remove the effects of windowing and the m-ch dynamic range control values applied in the frequency domain and readjust the dynamic range for 2-channel output.

Abstract: A longest common subprefix of two binary words p1 and p2 is identified based on bit strings ip1 and ip2 which are extensions of p1 and p2, and binary words n1 and n2 that define the length of p1 and p2. The bit strings and words are processed to set a “greater” output if p1>p2 and to set an “equal” output if p1=p2. A mask having a consecutive string of most significant bits having a first logical value is constructed to identify the matching subprefixes of p1 and p2.