Abstract: The present invention provides a method for forming interconnect lines and conductors and passive devices in the fabrication of an integrated circuit. A gap is created in the patterning of a first layer. The gap is filled by a dielectric material so that an encapsulated conduit is formed in the gap. The encapsulated conduit is filled with a conductor by chemical vapor deposition processes or other deposition processes, the filling facilitated by forming via holes to intersect the conduit, and then filling the via holes. The conductor filled conduit can be used as a resistor, fuse, inductor, or capacitor.

Abstract: A method of finding an optically periodic structure in a cell layer of an integrated circuit design includes receiving as input a physical representation of a cell layer of an integrated circuit design, finding reference coordinates of a selected portion of the cell layer from the physical representation of a cell layer, selecting an initial element located nearest to the reference coordinates, and constructing a base structure that includes the initial element and a minimum number of elements in the physical representation of the cell layer wherein the base structure may be replicated at an X-offset and a Y-offset to fill the entire selected portion so that for each element in each replica of the base structure there is an identical element at identical coordinates in the physical representation of the cell layer.

Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.

Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.

Abstract: A method for communicating on a SCSI bus permits out-of-band addressing and communication for normally non-addressable devices such as SCSI expanders and terminators. The method remaps 18 SCSI data lines for out-of-band operation and manipulates no more than those data lines. Some of the data lines are remapped for purposes of out-of-band signaling and data transfers. Advantageously, manipulation of only the SCSI data lines prevents the possible response of a device on the SCSI network that does not support the out-of-band operations. Accordingly, the disclosed method is backward compatible with existing SCSI networks while allowing implementation of devices having the increased functionality of out-of-band communication.

Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.

Abstract: Different dynamic range control values are applied to the 2-channel and m-channel outputs without repeating the inverse transform of the audio samples. First, m-channel dynamic range control values are applied to audio samples in the frequency domain (“frequency samples” or “frequency coefficients”). The frequency samples are then inverse transformed to generate audio samples in the time domain (“time samples”). The time samples are duplicated to two sets where the 2-channel dynamic range control values are applied to one set of time samples. 2-channel dynamic range control values include 2-channel final scales that, when multiplied with the first set of time samples, at least partially remove the effects of the m-channel dynamic range control and readjust the dynamic range for 2-channel output. The first set and the second set are then windowed.

Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits comprises a staircase of vias and traces arranged for maximum test coverage. The staircase may be combined with several functional cells to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of manufacturing process. The accessibility of many testing methods allows an engineer to quickly find root cause failures and thus make improvements to the manufacturing process.

Abstract: A method and apparatus for estimating the length of a transmission line is provided. The transmission line extends between a transmitter and a receiver and has a low-pass filter characteristic and an impulse response. The method and apparatus receive a data signal from the transmission line at the receiver and estimate the length of the transmission line as a function of the received data signal and the impulse response.

Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.

Abstract: The present invention is directed to a system and method for parallel configurable IP design. In an aspect of the present invention, a method may include receiving input parameters for a configuration by a common IP development environment. A unique combination of input parameters from the received input parameters is identified. At least one unique runtime file of the common IP development environment is initiated. The unique runtime file is derived from a common set of IP deliverables of the common IP development environment. At least one unique output file from the initiated unique runtime file is generated. The initiated unique runtime file and generated unique output file are unique so as to enable parallel implementation of the configuration specified by the received input parameter with at least one other configuration by the common IP development environment.

Abstract: An apparatus (22) for reducing noise in a tracking error signal receives input signals from an array (5) of photodetectors, each input signal indicating the amount of laser light incident on the corresponding photodetector reflected from an optical disc. The input signals from diagonal pairs of photodetectors are summed and then filtered and digitized to produce a pair of digital input signals. A signal difference generator (20) produces first and second difference signals when either the first or the second digital input signals are received. The first and second difference signals are received by a programmable timing element having a user programmable device (41) and a signal limiting device (32, 33, 34, 35) for limiting the duration of the first or second difference signals provided at respective first or second outputs of the programmable timing element to a user programmable maximum value.

Abstract: A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.

Abstract: An improved process simulation system for simulating results of fabrication process for a semiconductor device design is disclosed. According to the method and system disclosed herein, the process simulator receives processing parameters and mask data for at least two masks as input, and simulates results of the fabrication process such that an aerial image is generated for each layer of the device that was simulated. After generating the aerial images, the process simulator superimposes the aerial images to create a composite image. An operator is then allowed to misalign at least one of the images in relation to the other images based on one or more offset values. The composite image showing the misalignment is then displayed, allowing the operator to view nominal process capability as well as process fluctuations prior to fabrication of the semiconductor device.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract: The present invention provides a method and apparatus for providing dual-port capability to an SRAM array. The internal nodes of two single-port memory cells are connected to each other through metal-layer programming to form a dual-port memory cell. In a preferred embodiment, a split word line design is used for each single-port memory cell, to facilitate dual-port memory access while minimizing the need for IC layout space. An additional benefit of the present invention is that it allows “slices” of a memory array to be converted into dual-port memory, so as to allow both single-port and dual-port memory cells in the same memory array.

Abstract: The present invention is directed to magnetoresistive memory and data storage devices. A system for providing distributed functionality in an electronic environment includes a plurality of platforms suitable for providing a logic function. The platforms include embedded programmable logic, and MRAM memory, the logic and MRAM memory communicatively coupled via an interconnect.

Abstract: A semiconductor substrate having multiple signal voltage power supplies is provided. The substrate may include a signal voltage power ring separated into segmented voltage supply connections laterally spaced across the upper surface of the substrate. In addition, the substrate may include a voltage supply plane formed within the substrate. The voltage supply plane may be separated into segmented planes. Vias may electrically connect the segmented voltage supply connections to the segmented planes. In an embodiment, at least 2 of the segmented planes may have different voltage supplies. For example, each of the segmented voltage supply connections are configurable to supply power to a portion of input/output drivers of an integrated circuit. Voltage supplies of the segmented planes may be determined based on voltage requirements of the portions of the input/output drivers.

Abstract: A method of forming an electrical contact on a surface of a substrate. A first layer of a first electrically conductive material is formed on the surface of the substrate, where the first layer is formed in a substantially contiguous sheet across the surface of the substrate. A non electrically conductive masking layer is applied to the first layer, where the masking layer leaves exposed first portions of the first layer and covers second portions of the first layer. The substrate is immersed in a first electrolytic plating bath, and a first electrical potential is applied between the first layer and the first electrolytic plating bath, thereby causing the formation of a second layer of a second electrically conductive material on the exposed first portions of the first layer.