Patents Assigned to LSI Logic
  • Solder mask on bonding ring
    Patent number: 6777803
    Abstract: An improvement to an integrated circuit package substrate of the type that has a bonding ring with an exposed upper surface, where a first portion of the exposed upper surface is for receiving a molding compound and a second portion of the exposed upper surface is for receiving an electrical connection. A solder mask is formed on the first portion of the exposed upper surface of the bonding ring.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: August 17, 2004
    Assignee: LSI Logic Corporation
    Inventors: Maurice Othieno, Aritharan Thurairajaratnam, Manickam Thavarajah, Pradip D. Patei, Severino A. Legaspi, Jr.
  • High speed wafer sort and final test
    Patent number: 6777971
    Abstract: A semiconductor device which receives and transmits data at high speed is tested at operational speed at wafer sort. A probe card includes a high-speed interconnect that couples probe output bonding pads to probe input bonding pads. The high-speed interconnect connects a respective output of a transmitter in the die to a respective input of a receiver in the die while the probe card is connected to the die. A built in self test circuit in the die generates test patterns and compares them for accuracy. The test patterns are routed on the high-speed interconnect from the output of the transmitter to the input of the receiver allowing the data path through the receiver and transmitter in the die to be tested at operational speed before the die is assembled into a package.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: August 17, 2004
    Assignee: LSI Logic Corporation
    Inventors: Mohan Kirloskar, Albert Alcorn
  • Multi-step process for forming a barrier film for use in copper layer formation
    Publication number: 20040157425
    Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate in a processing chamber, the substrate having a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer is formed on the first barrier layer. The second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum. A copper seed layer is formed on the second barrier layer and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization.
    Type: Application
    Filed: February 3, 2004
    Publication date: August 12, 2004
    Applicant: LSI Logic Corporation
    Inventors: Wilbur G. Catabay, Zhihai Wang, Ping Li
  • Method and structure for forming dielectric layers having reduced dielectric constants
    Patent number: 6774057
    Abstract: The present invention is directed to a semiconductor structure including a semiconductor substrate having at least one overlying layer formed thereon. The at least one overlying layer including at least one layer of dielectric material. The at least one layer of dielectric material including a protected region having a first dielectric constant and another porous region having a second dielectric constant wherein the value for the second dielectric constant is less than the first dielectric constant. The porous region having been formed by the implantation of a porosity inducing material into the porous region and subsequent annealing. A method for forming such structures is also included.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Hong-Qiang Lu, Wei-Jen Hsia, Wilbur G. Catabay
  • Web-based interface with defect database to view and update failure events
    Patent number: 6775630
    Abstract: The present invention is directed to a system and method for providing access to semiconductor manufacturing information. The present invention system and method allows users to interface with semiconductor characteristic data and to data associated with manufacturing conditions over a network. The system includes at least one input device for entering manufacturing data. A data storage device capable of storing the database of manufacturing data, including semiconductor characteristic data and manufacturing conditions is networked to the at least one input device. A plurality of remote devices suitable for interfacing with the data are networked to the storage device, such that the manufacturing data is provided to a website for access upon occurrence of failure event.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Nima A. Behkami, James W. Seale, Newell E. Chiesl, Mark A. Giewont, Robert B. Powell
  • Chip design method for designing integrated circuit chips with embedded memories
    Patent number: 6775811
    Abstract: A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Viswanathan Lakshmanan, Michael Josephides, Tom R. O'Brien, David A. Morgan
  • Device parameter and gate performance simulation based on wafer image prediction
    Patent number: 6775818
    Abstract: A circuit, gate, or device parameter simulation includes data on the initial conditions of manufacture, including illumination conditions on a stepper, material parameters for processing conditions, and chip layout. Optical effects and processing tolerances may be accounted for in the simulation of the final device performance characteristics. The circuit, gate, or device parameter simulation may incorporate optical proximity code software. Simulated active and passive components are generated by the circuit, gate, or device parameter simulation from the simulated patterned layers on the substrate. Feedback may be provided to the circuit, gate, or device parameter simulation to optimize performance.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Kunal Taravade, Neal Callan, Nadya Strelkova
  • Convoluted EMC seal for subsystem CRU's in advanced controller based subsystems
    Patent number: 6775131
    Abstract: A sealing mechanism for a customer replaceable unit (CRU) within a computer system is provided. The sealing mechanism comprises a faceplate for the CRU, wherein insertion and extraction latches are recessed into a trench within that faceplate. The backside of the faceplate has a protruding rim around the perimeter. The rim engages a groove in the subsystem enclosure, which surrounds the aperture that the CRU engages. Since the faceplate incorporates a perimeter ridge and a trench structure, the interacting groove follows the contour of the trench. Thus the rim and groove both trace the faceplate trench around the faceplate. The groove in the subsystem enclosure has an entrenched section at both ends of the receptacle perimeter that accommodate sections of the faceplate rim that trace the trench in the faceplate.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventor: George E. Hanson
  • Frequency division multiple access system searching
    Patent number: 6775261
    Abstract: Channels are acquired and/or searched in a frequency division multiple access (FDMA) wireless system. Initially, a signal that includes a block of FDMA channels is received and filtered so as to select a frequency band that includes the block of FDMA channels. The filtered signal is then processed to obtain measures of certain frequency components in the filtered signal, and a power estimate for at least one of the FDMA channels is calculated based on at least one of frequency component measures.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventor: Brian C. Banister
  • High density data write strategy
    Patent number: 6775218
    Abstract: A system and method are disclosed for recording information on a phase change medium is disclosed. The method includes irradiating a region of the phase change medium with a first dose of laser energy. A first portion of the region is irradiated with a second dose of laser energy in a manner that causes the first portion of the region irradiated with the second dose of laser energy to be in a different state than a second portion of the region that is not irradiated by the second dose of laser energy.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Michael P. O'Neill, Terrence L. Wong, David K. Warland, Kunjithapatham Balasubramanian, Matthew C. Bashaw, Timothy Learmonth, Gregory A. McDermott, Raghuram Narayan, Judith C. Powelson, Ting Zhou
  • Fast sampling test bench
    Patent number: 6775798
    Abstract: An apparatus and method for using the apparatus for reducing analysis time of integrated circuits. The apparatus includes an integrated logic analyzer inserted in a substrate containing the integrated circuit and means for accelerating circuit analysis using the integrated logic analyzer. The means may be selected from the group consisting of a high speed sampling circuit coupled to the integrated logic analyzer and an on-board circuit testing and analysis apparatus including the integrated logic analyzer. Use of the apparatus enables lower production costs by speeding up circuit analysis as well as providing analysis of high speed circuits in a cost effective manner.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventor: Daniel R. Watkins
  • On-chip graded index of refraction optical waveguide and damascene method of fabricating the same
    Patent number: 6775453
    Abstract: A graded index of refraction optical waveguide is formed in interlayer dielectric material located above a substrate an integrated circuit-like structure. The waveguide includes a refractive layer of optically transmissive material surrounding a core of optically transmissive material within a trench in the dielectric material. The material of the core has a higher index of refraction than the refractive layer and the material of the refractive layer has a higher index of refraction than the dielectric material. More than one refractive layer may also be formed in the trench, with the inner refractive layer having an index of refraction higher than the outer refractive layer and less than the core.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventors: Verne C. Hornbeck, Derryl D. J. Allman
  • Power rails glitch noise insensitive charge pump
    Patent number: 6774730
    Abstract: A the charge pump suitable for use in phase-locked loop (PLL) circuits employed by mixed signal integrated circuits (IC) is disclosed. The PLL charge pump includes a constant current source that generates constant current source references with high power supply rejection for the P- and N-channel devices of the charge pump. Pass-gate transistors are inserted between the output terminals and the drains of the respective P- and N-channel devices. The switching transients power supply and ground are confined to the turn on/off leads of the pass-gate transistors and, thus, are isolated from the constant current source P- and N-channel devices. In exemplary embodiments of the invention, the constant current of the P- and N-channel devices may be made programmable and used for controlling the range of the current controlled oscillator of the PLL circuit.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventor: Frank Gasparik
  • Bandwidth management
    Patent number: 6774952
    Abstract: The invention relates to a method and apparatus for vertically scaling a video picture comprising receiving and storing lines of a video frame of a video picture, reading lines of the frame into linestores, applying the lines to a vertical filter and providing an output video line as a function of the lines. Reading the lines of the frame into linestores comprises reading M lines of each successive 2nd line of the frame lines into the linestores. Following generation of the output video line, a further X lines are read from the framestore into the linestores to provide a further set of M lines in the linestores. The M lines are applied to the vertical filter to provide a further output video line as a function of the lines.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: August 10, 2004
    Assignee: LSI Logic Corporation
    Inventor: Martin John Ratcliffe
  • Apparatus and/or method for variable data rate conversion
    Publication number: 20040151267
    Abstract: An apparatus generally comprising a first circuit, a second circuit and a third circuit is shown. The first circuit may be configured to generate a phase signal by dividing each cycle of an output clock into a plurality of phase values. The second circuit may be configured to generate an intermediate data signal by interpolating an input data signal sampled with an input clock in response to the phase signal and the output clock. The third circuit configured to generate an output data signal by sampling the intermediate data signal with the output clock.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Applicant: LSI LOGIC CORPORATION
    Inventors: Dean L. Raby, Robert Caulfield
  • Inverting level shifter with start-up circuit
    Patent number: 6771110
    Abstract: An apparatus comprising a method for providing inverting level shifting, comprising the steps of (A) receiving an input signal having a first predetermined voltage level, (B) controlling a voltage level of said input signal and (C) generating an output signal having a second predetermined voltage level, wherein step (C) provides full scale output voltages between a first supply and a second supply.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventors: Sean A. Golliher, Scott C. Savage, John L. Mcnitt
  • Socketless/boardless test interposer card
    Patent number: 6771085
    Abstract: An interposer card used during qualification tests on integrated circuit packages is disclosed that eliminates the need for sockets and custom boards. The interposer card includes pads for mounting the I/Os of a test package; edge card connectors for connecting the interposer card directly to a test board and for performing bias testing on the test package; and pads for replicating the test package I/Os for connecting the interposer card to an automated electrical testing (ATE) system for performing ATE tests on the test package.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventor: Carlo Grilletto
  • Data timeline management using snapshot volumes
    Patent number: 6771843
    Abstract: In a computerized data storage system, snapshot volumes are used to preserve the state of the base volume at various points in time, and later-formed snapshot volumes are retained after rolling back an earlier-formed snapshot volume into the base volume. During the rollback, data writes to the base volume are copied to the later-formed snapshot volumes when necessary to continue to preserve the states of the base volume represented by the later-formed snapshot volumes.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventors: Robin Huber, Donald R. Humlicek
  • SCSI phase specific bus reset generator
    Patent number: 6772329
    Abstract: The present invention is a bus reset generator capable of asserting a reset upon detection of a desired phase. The bus reset generator may analyze control signals from a bus, and based upon the control signals may determine the current phase of the bus. If the current phase is the desired phase for a reset, then a reset may be asserted. If the current phase is not the desired phase, the bus reset generator may continue to find the desired phase.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventor: Andrew Hadley
  • Methods and apparatus for managing cached CRC values in a storage controller
    Patent number: 6772289
    Abstract: A CRC value cache architecture and methods of operation of same to reduce overhead processing associated with managing a CRC value cache memory. The invention first provides for transferring from system memory to CRC value cache memory all CRC values for all sub-blocks of a data block in response to access to a first CRC value for a first sub-block. This reduces overhead processing to arbitrate for control of the system memory for each CRC value for each sub-block of a block. The invention additionally provides that a separate cache table is maintained corresponding to each device within the storage controller that requests CRC values. Each of the multiple cache entry tables is therefore shorter and more rapidly searched as compared to prior techniques thereby further reducing overhead processing to manage the cached CRC values.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: August 3, 2004
    Assignee: LSI Logic Corporation
    Inventor: Brian E. Corrigan