Abstract: An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.

Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.

Abstract: A method for motion estimation comprising the steps of (A) determining whether a cost of encoding one or more prediction parameters for a current search position is less than a current best cost, (B) when the cost of encoding the one or more prediction parameters for the current search position is less than the current best cost, updating the current best cost if the current best cost is greater than or equal to a sum of the cost for encoding the one or more prediction parameters for the current search position and a distortion measurement for the current search position and (C) ending the search when the current best cost is less than or equal to the cost of encoding the one or more prediction parameters for the current search position and less than a minimum cost for encoding one or more prediction parameters for one or more remaining search positions.

Abstract: A method for managing data movement in a multi-level cache system having a primary cache and a secondary cache. The method includes determining whether an unallocated space of the primary cache has reached a minimum threshold; selecting at least one outgoing data block from the primary cache when the primary cache reached the minimum threshold; initiating a de-stage process for de-staging the outgoing data block from the primary cache; and terminating the de-stage process when the unallocated space of the primary cache has reached an upper threshold. The de-stage process further includes determining whether a cache hit has occurred in the secondary cache before; storing the outgoing data block in the secondary cache when the cache hit has occurred in the secondary cache before; generating and storing metadata regarding the outgoing data block; and deleting the outgoing data block from the primary cache.

Abstract: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.

Abstract: Systems and methods herein provide for load balancing Fiber Channel traffic. In this regard, a Fiber Channel load balancer may be operable to monitor Fiber Channel paths coupled to a host bus adapter and determine the speeds of the Fiber Channel ports within the Fiber Channel paths. The Fiber Channel load balancer may also be operable to determine certain characteristics of the Fiber Channel traffic being passed over the Fiber Channel paths. For example, a load balancer may determine Fiber Channel traffic sizes of pending requests and, based in part on the traffic sizes and operable normalized speeds of the Fiber Channel ports, adaptively route the pending original traffic across the Fiber Channel ports.

Abstract: Various embodiments of the present invention provide systems and methods for adaptive channel bit density estimation. For example, various embodiments of the present invention provide methods for adaptively estimating channel bit density. Such methods include providing a storage medium (178) that includes information corresponding to a process data set, and accessing the process data set from the storage medium (505). A first channel bit density estimate (535) is computed based at least in part on a first portion of the process data set (520-530), and a second channel bit density estimate (535) is calculated based at least in part on the first portion of the process data set, a second portion of the process data set (520-530) and the first channel bit density estimate (535).

Abstract: A metallic reflector device having one or an array of individual reflector elements for positioning over a corresponding one or array of light sources, preferably comprising one or more light emitting diodes (LEDs). The metallic reflector device includes a planar base and a plurality of the reflector elements. The planar base has one or a plurality of apertures, each aperture having an edge that defines a proximal rim of the reflector element. Each reflector element includes an annular sidewall having an inner surface that extends from the proximal annular rim to a distal annular rim. The proximal annular rim defines a first opening through which direct and reflected light from a light source is emitted. The distal annular rim defines a second opening through which the light source is disposed. The inner surface of the annular sidewall is formed from the material of the planar sheet by mechanically deforming the planar sheet, such as by stamping or drawing.

Abstract: A lighting device having a support module comprising a disk for supporting LEDs and having an outer perimeter with a curved portion and a housing with an inner surface having a curved portion configured to receive the curved portion of the support module disk so that the disk can be aimed by external adjustment devices with the curved portions of the disk and housing remaining in contact. The external adjustment device facilitates aiming of the disk without the need to open the sealed LED module. Heat from the LEDs and/or LED mounting assembly can be transferred via the contact of the curved surfaces to the outside air while the module is tilted, e.g., up to 15 degrees, or more, from vertical.

Abstract: An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.

Abstract: Systems and methods for reducing network performance degradation by assigning caching priorities to one or more states of a state machine are disclosed herein. In one embodiment, the method comprises storing, in a memory, a state machine corresponding to one or more patterns to be detected in a data stream, wherein the state machine comprises a plurality of states, generating a test data stream based on the one or more patterns, traversing the state machine with the test data stream, determining a respective hit quantities associated with each of the plurality of states, the hit quantities each indicating a number of accesses to a corresponding state by the traversing, and associating a caching priority to at least some of the plurality of states based on the hit quantities of the respective states.

Abstract: Various embodiments of the present invention provide systems and methods for data equalization. For example, various embodiments of the present invention provide methods for generating equalization data. The method includes inputting N bits of an equalization data pattern into respective stages of a shift register, wherein inputting the N bits occurs synchronous to a system data clock having a system data rate, and shifting the N bits of equalization data to next adjacent next stages of the shift register synchronous to an equalization data clock having an equalization data rate N times the system data rate.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes a summation circuit, a data detector circuit, an error feedback circuit, and an error calculation circuit. The summation circuit subtracts a low frequency offset feedback from an input signal to yield a processing output. The data detector circuit applies a data detection algorithm to a derivative of the processing output and provides an ideal output. The error feedback circuit includes a conditional subtraction circuit that conditionally subtracts an interim low frequency offset correction signal from a delayed version of the derivative of the processing output to yield an interim factor. The error calculation circuit generates an interim low frequency offset correction signal based at least in part on the interim factor and a derivative of the ideal output.

Abstract: An embodiment of the present invention is disclosed to include a hard disk drive allowing for access by two hosts to a device. Further disclosed are embodiments for reducing the delay and complexity of the SATA disk drive.

Abstract: A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.

Abstract: Methods, apparatus, and systems for generating bit-wise path equivalency information corresponding to 1T decision nodes in a soft output Viterbi algorithm (“SOVA”) decoder operating with an nT clock signal. An add, compare, select circuit (ACS) of the SOVA generates decision data for decision nodes 1T through nT responsive to each nT clock signal pulse. The decision data is applied to corresponding 1T through nT path equivalency detector circuits to generate 1T through nT path equivalency information for generation of soft output signals corresponding to the 1T through nT decision data.

Abstract: A method for transcoding from an MPEG-2 format to an H.264 format is disclosed. The method generally comprises the steps of (A) decoding an input video stream in the MPEG-2 format to generate a plurality of macroblocks; (B) determining a plurality of indicators from a pair of the macroblocks, the pair of the macroblocks being vertically adjoining; and (C) coding the pair of the macroblocks into an output video stream in the H.264 format using one of (i) a field mode coding and (ii) a frame mode coding as determined from the indicators.

Abstract: A first Network Interface Controller operates in a low power mode. The first Network Interface Controller transitions from low power mode to a power-up sequence if a sleep packet in not received from a second Network Interface Controller at the first Network Interface Controller within a predetermined time threshold.

Abstract: Methods and systems for data reconstruction following drive failures may include: storing data across two or more drives in one or more data stripes, each data stripe including two or more drive extents; detecting a degradation of a drive containing a drive extent associated with a first data stripe; assigning a reconstruction priority to the drive extent associated with the first data stripe; detecting a degradation of a drive containing a drive extent associated with a second data stripe; and assigning a reconstruction priority to the drive extent associated with the second data stripe.